Search

Do H. Yoo

Examiner (ID: 19244)

Most Active Art Unit
2511
Art Unit(s)
2818, 2502, 2824, 2511
Total Applications
794
Issued Applications
686
Pending Applications
18
Abandoned Applications
90

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 3952628 [patent_doc_number] => 05873001 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-02-16 [patent_title] => 'Method for rapid expansion of multi-byte sorting weights table to include user supplied sorting weights' [patent_app_type] => 1 [patent_app_number] => 8/843630 [patent_app_country] => US [patent_app_date] => 1997-04-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 14 [patent_no_of_words] => 3227 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/873/05873001.pdf [firstpage_image] =>[orig_patent_app_number] => 843630 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/843630
Method for rapid expansion of multi-byte sorting weights table to include user supplied sorting weights Apr 9, 1997 Issued
Array ( [id] => 3888023 [patent_doc_number] => 05838962 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-11-17 [patent_title] => 'Interrupt driven dynamic adjustment of branch predictions' [patent_app_type] => 1 [patent_app_number] => 8/840080 [patent_app_country] => US [patent_app_date] => 1997-04-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 5665 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/838/05838962.pdf [firstpage_image] =>[orig_patent_app_number] => 840080 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/840080
Interrupt driven dynamic adjustment of branch predictions Apr 8, 1997 Issued
Array ( [id] => 3818375 [patent_doc_number] => 05854920 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-12-29 [patent_title] => 'Method and apparatus for manipulating a carry/borrow bit to numerically adjust and immediate value of an instruction during execution' [patent_app_type] => 1 [patent_app_number] => 8/835371 [patent_app_country] => US [patent_app_date] => 1997-04-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 10 [patent_no_of_words] => 2893 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 170 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/854/05854920.pdf [firstpage_image] =>[orig_patent_app_number] => 835371 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/835371
Method and apparatus for manipulating a carry/borrow bit to numerically adjust and immediate value of an instruction during execution Apr 6, 1997 Issued
Array ( [id] => 4042826 [patent_doc_number] => 05903780 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-05-11 [patent_title] => 'Data sorting device having multi-input comparator comparing data input from latch register and key value storage devices' [patent_app_type] => 1 [patent_app_number] => 8/834738 [patent_app_country] => US [patent_app_date] => 1997-04-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 11 [patent_no_of_words] => 9163 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/903/05903780.pdf [firstpage_image] =>[orig_patent_app_number] => 834738 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/834738
Data sorting device having multi-input comparator comparing data input from latch register and key value storage devices Apr 2, 1997 Issued
Array ( [id] => 4057635 [patent_doc_number] => 05996065 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-11-30 [patent_title] => 'Apparatus for bypassing intermediate results from a pipelined floating point unit to multiple successive instructions' [patent_app_type] => 1 [patent_app_number] => 8/831473 [patent_app_country] => US [patent_app_date] => 1997-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 1652 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 55 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/996/05996065.pdf [firstpage_image] =>[orig_patent_app_number] => 831473 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/831473
Apparatus for bypassing intermediate results from a pipelined floating point unit to multiple successive instructions Mar 30, 1997 Issued
Array ( [id] => 4064902 [patent_doc_number] => 05870582 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-02-09 [patent_title] => 'Method and apparatus for completion of non-interruptible instructions before the instruction is dispatched' [patent_app_type] => 1 [patent_app_number] => 8/829671 [patent_app_country] => US [patent_app_date] => 1997-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 6354 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/870/05870582.pdf [firstpage_image] =>[orig_patent_app_number] => 829671 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/829671
Method and apparatus for completion of non-interruptible instructions before the instruction is dispatched Mar 30, 1997 Issued
Array ( [id] => 4040675 [patent_doc_number] => 05884071 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-03-16 [patent_title] => 'Method and apparatus for decoding enhancement instructions using alias encodings' [patent_app_type] => 1 [patent_app_number] => 8/829430 [patent_app_country] => US [patent_app_date] => 1997-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3900 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/884/05884071.pdf [firstpage_image] =>[orig_patent_app_number] => 829430 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/829430
Method and apparatus for decoding enhancement instructions using alias encodings Mar 30, 1997 Issued
Array ( [id] => 4010839 [patent_doc_number] => 05920875 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-07-06 [patent_title] => 'Tail compression of a sparse log stream of a computer system' [patent_app_type] => 1 [patent_app_number] => 8/827292 [patent_app_country] => US [patent_app_date] => 1997-03-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 5075 [patent_no_of_claims] => 44 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/920/05920875.pdf [firstpage_image] =>[orig_patent_app_number] => 827292 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/827292
Tail compression of a sparse log stream of a computer system Mar 27, 1997 Issued
Array ( [id] => 3969225 [patent_doc_number] => 05956735 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-09-21 [patent_title] => 'System of compressing the tail of a sparse log stream of a computer system' [patent_app_type] => 1 [patent_app_number] => 8/827558 [patent_app_country] => US [patent_app_date] => 1997-03-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 4434 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/956/05956735.pdf [firstpage_image] =>[orig_patent_app_number] => 827558 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/827558
System of compressing the tail of a sparse log stream of a computer system Mar 27, 1997 Issued
Array ( [id] => 4029679 [patent_doc_number] => 05963723 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-10-05 [patent_title] => 'System for pairing dependent instructions having non-contiguous addresses during dispatch' [patent_app_type] => 1 [patent_app_number] => 8/827076 [patent_app_country] => US [patent_app_date] => 1997-03-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 11 [patent_no_of_words] => 6056 [patent_no_of_claims] => 41 [patent_no_of_ind_claims] => 12 [patent_words_short_claim] => 53 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/963/05963723.pdf [firstpage_image] =>[orig_patent_app_number] => 827076 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/827076
System for pairing dependent instructions having non-contiguous addresses during dispatch Mar 25, 1997 Issued
Array ( [id] => 3924088 [patent_doc_number] => 05938766 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-08-17 [patent_title] => 'System for extending functionality of a digital ROM using RAM/ROM jump tables and patch manager for updating the tables' [patent_app_type] => 1 [patent_app_number] => 8/822773 [patent_app_country] => US [patent_app_date] => 1997-03-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 4695 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 179 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/938/05938766.pdf [firstpage_image] =>[orig_patent_app_number] => 822773 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/822773
System for extending functionality of a digital ROM using RAM/ROM jump tables and patch manager for updating the tables Mar 20, 1997 Issued
Array ( [id] => 3967680 [patent_doc_number] => 05983344 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-11-09 [patent_title] => 'Combining ALU and memory storage micro instructions by using an address latch to maintain an address calculated by a first micro instruction' [patent_app_type] => 1 [patent_app_number] => 8/820576 [patent_app_country] => US [patent_app_date] => 1997-03-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 4740 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 268 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/983/05983344.pdf [firstpage_image] =>[orig_patent_app_number] => 820576 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/820576
Combining ALU and memory storage micro instructions by using an address latch to maintain an address calculated by a first micro instruction Mar 18, 1997 Issued
Array ( [id] => 4018524 [patent_doc_number] => 05924122 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-07-13 [patent_title] => 'Method for error recovery spinlock in asymmetrically accessed multiprocessor shared memory' [patent_app_type] => 1 [patent_app_number] => 8/818757 [patent_app_country] => US [patent_app_date] => 1997-03-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 7905 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/924/05924122.pdf [firstpage_image] =>[orig_patent_app_number] => 818757 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/818757
Method for error recovery spinlock in asymmetrically accessed multiprocessor shared memory Mar 13, 1997 Issued
Array ( [id] => 4427313 [patent_doc_number] => 06226736 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-05-01 [patent_title] => 'Microprocessor configuration arrangement for selecting an external bus width' [patent_app_type] => 1 [patent_app_number] => 8/813274 [patent_app_country] => US [patent_app_date] => 1997-03-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4331 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/226/06226736.pdf [firstpage_image] =>[orig_patent_app_number] => 813274 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/813274
Microprocessor configuration arrangement for selecting an external bus width Mar 9, 1997 Issued
Array ( [id] => 4167463 [patent_doc_number] => 06065113 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-05-16 [patent_title] => 'Circuits, systems, and methods for uniquely identifying a microprocessor at the instruction set level employing one-time programmable register' [patent_app_type] => 1 [patent_app_number] => 8/813887 [patent_app_country] => US [patent_app_date] => 1997-03-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 5088 [patent_no_of_claims] => 49 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/065/06065113.pdf [firstpage_image] =>[orig_patent_app_number] => 813887 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/813887
Circuits, systems, and methods for uniquely identifying a microprocessor at the instruction set level employing one-time programmable register Mar 6, 1997 Issued
Array ( [id] => 3778966 [patent_doc_number] => 05845112 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-12-01 [patent_title] => 'Method for performing dead-zone quantization in a single processor instruction' [patent_app_type] => 1 [patent_app_number] => 8/812774 [patent_app_country] => US [patent_app_date] => 1997-03-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 3965 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/845/05845112.pdf [firstpage_image] =>[orig_patent_app_number] => 812774 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/812774
Method for performing dead-zone quantization in a single processor instruction Mar 5, 1997 Issued
Array ( [id] => 4015201 [patent_doc_number] => 05925124 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-07-20 [patent_title] => 'Dynamic conversion between different instruction codes by recombination of instruction elements' [patent_app_type] => 1 [patent_app_number] => 8/810880 [patent_app_country] => US [patent_app_date] => 1997-03-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 6483 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/925/05925124.pdf [firstpage_image] =>[orig_patent_app_number] => 810880 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/810880
Dynamic conversion between different instruction codes by recombination of instruction elements Mar 4, 1997 Issued
Array ( [id] => 4022839 [patent_doc_number] => 05889934 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-03-30 [patent_title] => 'Data validation system for a group of data storage disks' [patent_app_type] => 1 [patent_app_number] => 8/805144 [patent_app_country] => US [patent_app_date] => 1997-02-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 4164 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/889/05889934.pdf [firstpage_image] =>[orig_patent_app_number] => 805144 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/805144
Data validation system for a group of data storage disks Feb 23, 1997 Issued
Array ( [id] => 3962003 [patent_doc_number] => 05974538 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-10-26 [patent_title] => 'Method and apparatus for annotating operands in a computer system with source instruction identifiers' [patent_app_type] => 1 [patent_app_number] => 8/804175 [patent_app_country] => US [patent_app_date] => 1997-02-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 18772 [patent_no_of_claims] => 85 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/974/05974538.pdf [firstpage_image] =>[orig_patent_app_number] => 804175 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/804175
Method and apparatus for annotating operands in a computer system with source instruction identifiers Feb 20, 1997 Issued
Array ( [id] => 4036850 [patent_doc_number] => 05968161 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-10-19 [patent_title] => 'FPGA based configurable CPU additionally including second programmable section for implementation of custom hardware support' [patent_app_type] => 1 [patent_app_number] => 8/797585 [patent_app_country] => US [patent_app_date] => 1997-02-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 2187 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 195 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/968/05968161.pdf [firstpage_image] =>[orig_patent_app_number] => 797585 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/797585
FPGA based configurable CPU additionally including second programmable section for implementation of custom hardware support Feb 6, 1997 Issued
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