| Application number | Title of the application | Filing Date | Status |
|---|
Array
(
[id] => 3515519
[patent_doc_number] => 05515318
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-05-07
[patent_title] => 'Method of evaluating the gate oxide of non-volatile EPROM, EEPROM and flash-EEPROM memories'
[patent_app_type] => 1
[patent_app_number] => 8/460540
[patent_app_country] => US
[patent_app_date] => 1995-06-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 9
[patent_no_of_words] => 3120
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 97
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/515/05515318.pdf
[firstpage_image] =>[orig_patent_app_number] => 460540
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/460540 | Method of evaluating the gate oxide of non-volatile EPROM, EEPROM and flash-EEPROM memories | Jun 1, 1995 | Issued |
Array
(
[id] => 3792613
[patent_doc_number] => 05818793
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-10-06
[patent_title] => 'Clock-synchronous semiconductor memory device'
[patent_app_type] => 1
[patent_app_number] => 8/457165
[patent_app_country] => US
[patent_app_date] => 1995-06-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 11
[patent_no_of_words] => 6208
[patent_no_of_claims] => 35
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 206
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/818/05818793.pdf
[firstpage_image] =>[orig_patent_app_number] => 457165
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/457165 | Clock-synchronous semiconductor memory device | May 31, 1995 | Issued |
Array
(
[id] => 3699075
[patent_doc_number] => 05604699
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-02-18
[patent_title] => 'Method of evaluating the dielectric layer of nonvolatile EPROM, EEPROM and flash-EEPROM memories'
[patent_app_type] => 1
[patent_app_number] => 8/454854
[patent_app_country] => US
[patent_app_date] => 1995-05-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 16
[patent_no_of_words] => 4454
[patent_no_of_claims] => 30
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 111
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/604/05604699.pdf
[firstpage_image] =>[orig_patent_app_number] => 454854
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/454854 | Method of evaluating the dielectric layer of nonvolatile EPROM, EEPROM and flash-EEPROM memories | May 30, 1995 | Issued |
Array
(
[id] => 3544727
[patent_doc_number] => 05557570
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-09-17
[patent_title] => 'Nonvolatile semiconductor memory device'
[patent_app_type] => 1
[patent_app_number] => 8/449750
[patent_app_country] => US
[patent_app_date] => 1995-05-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 16
[patent_figures_cnt] => 36
[patent_no_of_words] => 14914
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 260
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/557/05557570.pdf
[firstpage_image] =>[orig_patent_app_number] => 449750
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/449750 | Nonvolatile semiconductor memory device | May 24, 1995 | Issued |
| 08/450087 | METHOD AND STRUCTURE FOR RECOVERING SMALLER DENSITY MEMORIES FROM LARGER DENSITY MEMORIES | May 24, 1995 | Abandoned |
Array
(
[id] => 3697568
[patent_doc_number] => 05644527
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-07-01
[patent_title] => 'Semiconductor memory device'
[patent_app_type] => 1
[patent_app_number] => 8/448756
[patent_app_country] => US
[patent_app_date] => 1995-05-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 13
[patent_no_of_words] => 5648
[patent_no_of_claims] => 2
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 128
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/644/05644527.pdf
[firstpage_image] =>[orig_patent_app_number] => 448756
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/448756 | Semiconductor memory device | May 23, 1995 | Issued |
| 08/448322 | SENSING SCHEME FOR FLASH MEMORY WITH MULTILEVEL CELLS | May 22, 1995 | Abandoned |
Array
(
[id] => 3566168
[patent_doc_number] => 05544116
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-08-06
[patent_title] => 'Erase and program verification circuit for non-volatile memory'
[patent_app_type] => 1
[patent_app_number] => 8/444672
[patent_app_country] => US
[patent_app_date] => 1995-05-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 8
[patent_no_of_words] => 8939
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 136
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/544/05544116.pdf
[firstpage_image] =>[orig_patent_app_number] => 444672
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/444672 | Erase and program verification circuit for non-volatile memory | May 18, 1995 | Issued |
Array
(
[id] => 3536386
[patent_doc_number] => 05528546
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-06-18
[patent_title] => 'Erase and program verification circuit for non-volatile memory'
[patent_app_type] => 1
[patent_app_number] => 8/444771
[patent_app_country] => US
[patent_app_date] => 1995-05-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 8
[patent_no_of_words] => 8940
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 292
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/528/05528546.pdf
[firstpage_image] =>[orig_patent_app_number] => 444771
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/444771 | Erase and program verification circuit for non-volatile memory | May 18, 1995 | Issued |
Array
(
[id] => 3582414
[patent_doc_number] => 05539688
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-07-23
[patent_title] => 'Fast pre-programming circuit for floating gate memory'
[patent_app_type] => 1
[patent_app_number] => 8/444313
[patent_app_country] => US
[patent_app_date] => 1995-05-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 12
[patent_no_of_words] => 6590
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 194
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/539/05539688.pdf
[firstpage_image] =>[orig_patent_app_number] => 444313
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/444313 | Fast pre-programming circuit for floating gate memory | May 17, 1995 | Issued |
Array
(
[id] => 3520816
[patent_doc_number] => 05563822
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-10-08
[patent_title] => 'Fast flash EPROM programming and pre-programming circuit design'
[patent_app_type] => 1
[patent_app_number] => 8/444315
[patent_app_country] => US
[patent_app_date] => 1995-05-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 12
[patent_no_of_words] => 6592
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 172
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/563/05563822.pdf
[firstpage_image] =>[orig_patent_app_number] => 444315
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/444315 | Fast flash EPROM programming and pre-programming circuit design | May 17, 1995 | Issued |
Array
(
[id] => 3715970
[patent_doc_number] => 05654929
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-08-05
[patent_title] => 'Refresh strategy for DRAMs'
[patent_app_type] => 1
[patent_app_number] => 8/527950
[patent_app_country] => US
[patent_app_date] => 1995-05-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 6
[patent_no_of_words] => 2134
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 110
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/654/05654929.pdf
[firstpage_image] =>[orig_patent_app_number] => 527950
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/527950 | Refresh strategy for DRAMs | May 13, 1995 | Issued |
| 08/440046 | SYSTEM FOR CONSTANT FIELD ERASURE IN A FLASH EPROM | May 11, 1995 | Abandoned |
Array
(
[id] => 3560921
[patent_doc_number] => 05572476
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-11-05
[patent_title] => 'Apparatus and method for determining the resistance of antifuses in an array'
[patent_app_type] => 1
[patent_app_number] => 8/431654
[patent_app_country] => US
[patent_app_date] => 1995-05-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 4368
[patent_no_of_claims] => 3
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 111
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/572/05572476.pdf
[firstpage_image] =>[orig_patent_app_number] => 431654
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/431654 | Apparatus and method for determining the resistance of antifuses in an array | May 1, 1995 | Issued |
Array
(
[id] => 3572903
[patent_doc_number] => 05526312
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-06-11
[patent_title] => 'Apparatus and method for determining the resistance of antifuses in an array'
[patent_app_type] => 1
[patent_app_number] => 8/433794
[patent_app_country] => US
[patent_app_date] => 1995-05-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 4365
[patent_no_of_claims] => 1
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 270
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/526/05526312.pdf
[firstpage_image] =>[orig_patent_app_number] => 433794
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/433794 | Apparatus and method for determining the resistance of antifuses in an array | May 1, 1995 | Issued |
Array
(
[id] => 3678554
[patent_doc_number] => 05600604
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-02-04
[patent_title] => 'System for allowing a simm module with asymmetric addressing to be utilized in a computer system'
[patent_app_type] => 1
[patent_app_number] => 8/431439
[patent_app_country] => US
[patent_app_date] => 1995-05-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 2310
[patent_no_of_claims] => 3
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 116
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/600/05600604.pdf
[firstpage_image] =>[orig_patent_app_number] => 431439
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/431439 | System for allowing a simm module with asymmetric addressing to be utilized in a computer system | Apr 30, 1995 | Issued |
Array
(
[id] => 3636535
[patent_doc_number] => 05621690
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-04-15
[patent_title] => 'Nonvolatile memory blocking architecture and redundancy'
[patent_app_type] => 1
[patent_app_number] => 8/430344
[patent_app_country] => US
[patent_app_date] => 1995-04-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 5405
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 109
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/621/05621690.pdf
[firstpage_image] =>[orig_patent_app_number] => 430344
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/430344 | Nonvolatile memory blocking architecture and redundancy | Apr 27, 1995 | Issued |
Array
(
[id] => 3518948
[patent_doc_number] => 05587949
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-12-24
[patent_title] => 'Method for programming an ETOX EPROM or flash memory when cells of the array are formed to store multiple bits of data'
[patent_app_type] => 1
[patent_app_number] => 8/429644
[patent_app_country] => US
[patent_app_date] => 1995-04-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 8
[patent_no_of_words] => 4630
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 355
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/587/05587949.pdf
[firstpage_image] =>[orig_patent_app_number] => 429644
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/429644 | Method for programming an ETOX EPROM or flash memory when cells of the array are formed to store multiple bits of data | Apr 26, 1995 | Issued |
| 08/423550 | BIT MAP ADDRESSING SCHEMES FOR FLASH MEMORY | Apr 16, 1995 | Abandoned |
| 08/423557 | BIT MAP ADDRESSING SCHEMES FOR FLASH MEMORY | Apr 16, 1995 | Abandoned |