Search

Do H. Yoo

Examiner (ID: 7566)

Most Active Art Unit
2511
Art Unit(s)
2824, 2818, 2502, 2511
Total Applications
794
Issued Applications
686
Pending Applications
18
Abandoned Applications
90

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 3953335 [patent_doc_number] => 05973969 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-10-26 [patent_title] => 'Defective memory cell address detecting circuit' [patent_app_type] => 1 [patent_app_number] => 9/138010 [patent_app_country] => US [patent_app_date] => 1998-08-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 4531 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 251 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/973/05973969.pdf [firstpage_image] =>[orig_patent_app_number] => 138010 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/138010
Defective memory cell address detecting circuit Aug 20, 1998 Issued
Array ( [id] => 4192068 [patent_doc_number] => 06038181 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-03-14 [patent_title] => 'Efficient semiconductor burn-in circuit and method of operation' [patent_app_type] => 1 [patent_app_number] => 9/136112 [patent_app_country] => US [patent_app_date] => 1998-08-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 6297 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 235 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/038/06038181.pdf [firstpage_image] =>[orig_patent_app_number] => 136112 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/136112
Efficient semiconductor burn-in circuit and method of operation Aug 17, 1998 Issued
Array ( [id] => 4045853 [patent_doc_number] => 05943272 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-08-24 [patent_title] => 'Circuit for sensing memory having a plurality of threshold voltages' [patent_app_type] => 1 [patent_app_number] => 9/124915 [patent_app_country] => US [patent_app_date] => 1998-07-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 10 [patent_no_of_words] => 2862 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/943/05943272.pdf [firstpage_image] =>[orig_patent_app_number] => 124915 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/124915
Circuit for sensing memory having a plurality of threshold voltages Jul 29, 1998 Issued
Array ( [id] => 3947275 [patent_doc_number] => 05940335 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-08-17 [patent_title] => 'Prioritizing the repair of faults in a semiconductor memory device' [patent_app_type] => 1 [patent_app_number] => 9/122426 [patent_app_country] => US [patent_app_date] => 1998-07-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 15 [patent_no_of_words] => 6549 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 159 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/940/05940335.pdf [firstpage_image] =>[orig_patent_app_number] => 122426 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/122426
Prioritizing the repair of faults in a semiconductor memory device Jul 23, 1998 Issued
Array ( [id] => 3970371 [patent_doc_number] => 05936910 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-08-10 [patent_title] => 'Semiconductor memory device having burn-in test function' [patent_app_type] => 1 [patent_app_number] => 9/120507 [patent_app_country] => US [patent_app_date] => 1998-07-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 3832 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/936/05936910.pdf [firstpage_image] =>[orig_patent_app_number] => 120507 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/120507
Semiconductor memory device having burn-in test function Jul 22, 1998 Issued
Array ( [id] => 4234274 [patent_doc_number] => 06011741 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-01-04 [patent_title] => 'Computer memory cards using flash EEPROM integrated circuit chips and memory-controller systems' [patent_app_type] => 1 [patent_app_number] => 9/121348 [patent_app_country] => US [patent_app_date] => 1998-07-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 20 [patent_no_of_words] => 6543 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 30 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/011/06011741.pdf [firstpage_image] =>[orig_patent_app_number] => 121348 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/121348
Computer memory cards using flash EEPROM integrated circuit chips and memory-controller systems Jul 22, 1998 Issued
Array ( [id] => 4012573 [patent_doc_number] => 05986968 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-11-16 [patent_title] => 'Clock-synchronous semiconductor memory device and access method thereof' [patent_app_type] => 1 [patent_app_number] => 9/113570 [patent_app_country] => US [patent_app_date] => 1998-07-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 11 [patent_no_of_words] => 6210 [patent_no_of_claims] => 46 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/986/05986968.pdf [firstpage_image] =>[orig_patent_app_number] => 113570 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/113570
Clock-synchronous semiconductor memory device and access method thereof Jul 9, 1998 Issued
Array ( [id] => 3962213 [patent_doc_number] => 05956273 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-09-21 [patent_title] => 'Fast flash EPROM programming and pre-programming circuit design' [patent_app_type] => 1 [patent_app_number] => 9/106525 [patent_app_country] => US [patent_app_date] => 1998-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 12 [patent_no_of_words] => 6591 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/956/05956273.pdf [firstpage_image] =>[orig_patent_app_number] => 106525 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/106525
Fast flash EPROM programming and pre-programming circuit design Jun 28, 1998 Issued
Array ( [id] => 4012330 [patent_doc_number] => 05986951 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-11-16 [patent_title] => 'Address signal storage circuit of data repair controller' [patent_app_type] => 1 [patent_app_number] => 9/102576 [patent_app_country] => US [patent_app_date] => 1998-06-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 6722 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 257 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/986/05986951.pdf [firstpage_image] =>[orig_patent_app_number] => 102576 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/102576
Address signal storage circuit of data repair controller Jun 22, 1998 Issued
09/102908 OUTPUT BUFFER OF SEMICONDUCTOR MEMORY DEVICE Jun 22, 1998 Issued
09/100407 DATA DETERMINING CIRCUITRY AND DATA DETERMINING METHOD Jun 18, 1998 Issued
Array ( [id] => 4096350 [patent_doc_number] => 06018486 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-01-25 [patent_title] => 'Reading method and circuit for dynamic memory' [patent_app_type] => 1 [patent_app_number] => 9/093210 [patent_app_country] => US [patent_app_date] => 1998-06-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 10 [patent_no_of_words] => 9375 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/018/06018486.pdf [firstpage_image] =>[orig_patent_app_number] => 093210 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/093210
Reading method and circuit for dynamic memory Jun 7, 1998 Issued
Array ( [id] => 4170014 [patent_doc_number] => 06104634 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-08-15 [patent_title] => 'Electrical programmable non-volatile memory integrated circuit with option configuration register' [patent_app_type] => 1 [patent_app_number] => 9/087415 [patent_app_country] => US [patent_app_date] => 1998-05-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 4050 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/104/06104634.pdf [firstpage_image] =>[orig_patent_app_number] => 087415 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/087415
Electrical programmable non-volatile memory integrated circuit with option configuration register May 28, 1998 Issued
Array ( [id] => 4078082 [patent_doc_number] => 06009023 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-12-28 [patent_title] => 'High performance DRAM structure employing multiple thickness gate oxide' [patent_app_type] => 1 [patent_app_number] => 9/084409 [patent_app_country] => US [patent_app_date] => 1998-05-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 10 [patent_no_of_words] => 5177 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/009/06009023.pdf [firstpage_image] =>[orig_patent_app_number] => 084409 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/084409
High performance DRAM structure employing multiple thickness gate oxide May 25, 1998 Issued
Array ( [id] => 3947184 [patent_doc_number] => 05940330 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-08-17 [patent_title] => 'Synchronous memory device having a plurality of clock input buffers' [patent_app_type] => 1 [patent_app_number] => 9/080411 [patent_app_country] => US [patent_app_date] => 1998-05-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 2544 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/940/05940330.pdf [firstpage_image] =>[orig_patent_app_number] => 080411 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/080411
Synchronous memory device having a plurality of clock input buffers May 17, 1998 Issued
Array ( [id] => 4026094 [patent_doc_number] => 05963497 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-10-05 [patent_title] => 'Dynamic random access memory system with simultaneous access and refresh operations and methods for using the same' [patent_app_type] => 1 [patent_app_number] => 9/080813 [patent_app_country] => US [patent_app_date] => 1998-05-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 7 [patent_no_of_words] => 5051 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 173 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/963/05963497.pdf [firstpage_image] =>[orig_patent_app_number] => 080813 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/080813
Dynamic random access memory system with simultaneous access and refresh operations and methods for using the same May 17, 1998 Issued
Array ( [id] => 3953314 [patent_doc_number] => 05973968 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-10-26 [patent_title] => 'Apparatus and method for write protecting a programmable memory' [patent_app_type] => 1 [patent_app_number] => 9/070710 [patent_app_country] => US [patent_app_date] => 1998-04-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 8517 [patent_no_of_claims] => 36 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/973/05973968.pdf [firstpage_image] =>[orig_patent_app_number] => 070710 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/070710
Apparatus and method for write protecting a programmable memory Apr 29, 1998 Issued
Array ( [id] => 4026084 [patent_doc_number] => 05963496 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-10-05 [patent_title] => 'Sense amplifier with zero power idle mode' [patent_app_type] => 1 [patent_app_number] => 9/064811 [patent_app_country] => US [patent_app_date] => 1998-04-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 10 [patent_no_of_words] => 4723 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 232 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/963/05963496.pdf [firstpage_image] =>[orig_patent_app_number] => 064811 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/064811
Sense amplifier with zero power idle mode Apr 21, 1998 Issued
09/063529 STAGGERED PIPELINE ACCESS SCHEME FOR SYNCHRONOUS RANDOM ACCESS MEM0RY Apr 20, 1998 Issued
Array ( [id] => 4144094 [patent_doc_number] => 06034881 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-03-07 [patent_title] => 'Transistor stack read only memory' [patent_app_type] => 1 [patent_app_number] => 9/060113 [patent_app_country] => US [patent_app_date] => 1998-04-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 1747 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/034/06034881.pdf [firstpage_image] =>[orig_patent_app_number] => 060113 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/060113
Transistor stack read only memory Apr 14, 1998 Issued
Menu