Search

Do H. Yoo

Examiner (ID: 19244)

Most Active Art Unit
2511
Art Unit(s)
2818, 2502, 2824, 2511
Total Applications
794
Issued Applications
686
Pending Applications
18
Abandoned Applications
90

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 9161 [patent_doc_number] => 07814298 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2010-10-12 [patent_title] => 'Promoting and appending traces in an instruction processing circuit based upon a bias value' [patent_app_type] => utility [patent_app_number] => 11/941883 [patent_app_country] => US [patent_app_date] => 2007-11-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 12 [patent_no_of_words] => 12482 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 59 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/814/07814298.pdf [firstpage_image] =>[orig_patent_app_number] => 11941883 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/941883
Promoting and appending traces in an instruction processing circuit based upon a bias value Nov 15, 2007 Issued
Array ( [id] => 4798851 [patent_doc_number] => 20080010437 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-01-10 [patent_title] => 'Unit for processing numeric and logic operations for use in central processing units (CPUS), multiprocessor systems, data-flow processors (DSPS), systolic processors and field programmable gate arrays (FPGAS)' [patent_app_type] => utility [patent_app_number] => 11/820780 [patent_app_country] => US [patent_app_date] => 2007-06-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 8309 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0010/20080010437.pdf [firstpage_image] =>[orig_patent_app_number] => 11820780 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/820780
Processor chip for reconfigurable data processing, for processing numeric and logic operations and including function and interconnection control units Jun 18, 2007 Issued
Array ( [id] => 4585221 [patent_doc_number] => 07849120 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-12-07 [patent_title] => 'Microprocessor with random number generator and instruction for storing random data' [patent_app_type] => utility [patent_app_number] => 11/616039 [patent_app_country] => US [patent_app_date] => 2006-12-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 18 [patent_no_of_words] => 17051 [patent_no_of_claims] => 45 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/849/07849120.pdf [firstpage_image] =>[orig_patent_app_number] => 11616039 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/616039
Microprocessor with random number generator and instruction for storing random data Dec 25, 2006 Issued
Array ( [id] => 8429 [patent_doc_number] => 07818358 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-10-19 [patent_title] => 'Microprocessor with random number generator and instruction for storing random data' [patent_app_type] => utility [patent_app_number] => 11/615994 [patent_app_country] => US [patent_app_date] => 2006-12-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 18 [patent_no_of_words] => 16708 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/818/07818358.pdf [firstpage_image] =>[orig_patent_app_number] => 11615994 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/615994
Microprocessor with random number generator and instruction for storing random data Dec 24, 2006 Issued
Array ( [id] => 329497 [patent_doc_number] => 07516305 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-04-07 [patent_title] => 'System and method for retiring approximately simultaneously a group of instructions in a superscalar microprocessor' [patent_app_type] => utility [patent_app_number] => 11/642625 [patent_app_country] => US [patent_app_date] => 2006-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 6886 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 399 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/516/07516305.pdf [firstpage_image] =>[orig_patent_app_number] => 11642625 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/642625
System and method for retiring approximately simultaneously a group of instructions in a superscalar microprocessor Dec 20, 2006 Issued
Array ( [id] => 336714 [patent_doc_number] => 07509480 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-03-24 [patent_title] => 'Selection of ISA decoding mode for plural instruction sets based upon instruction address' [patent_app_type] => utility [patent_app_number] => 11/636462 [patent_app_country] => US [patent_app_date] => 2006-12-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 10020 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/509/07509480.pdf [firstpage_image] =>[orig_patent_app_number] => 11636462 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/636462
Selection of ISA decoding mode for plural instruction sets based upon instruction address Dec 10, 2006 Issued
Array ( [id] => 268560 [patent_doc_number] => 07568089 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2009-07-28 [patent_title] => 'Flag management in processors enabled for speculative execution of micro-operation traces' [patent_app_type] => utility [patent_app_number] => 11/553458 [patent_app_country] => US [patent_app_date] => 2006-10-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 10977 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 166 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/568/07568089.pdf [firstpage_image] =>[orig_patent_app_number] => 11553458 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/553458
Flag management in processors enabled for speculative execution of micro-operation traces Oct 25, 2006 Issued
Array ( [id] => 248824 [patent_doc_number] => 07587585 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2009-09-08 [patent_title] => 'Flag management in processors enabled for speculative execution of micro-operation traces' [patent_app_type] => utility [patent_app_number] => 11/553453 [patent_app_country] => US [patent_app_date] => 2006-10-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 11278 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/587/07587585.pdf [firstpage_image] =>[orig_patent_app_number] => 11553453 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/553453
Flag management in processors enabled for speculative execution of micro-operation traces Oct 25, 2006 Issued
Array ( [id] => 268559 [patent_doc_number] => 07568088 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2009-07-28 [patent_title] => 'Flag management in processors enabled for speculative execution of micro-operation traces' [patent_app_type] => utility [patent_app_number] => 11/553455 [patent_app_country] => US [patent_app_date] => 2006-10-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 11429 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 191 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/568/07568088.pdf [firstpage_image] =>[orig_patent_app_number] => 11553455 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/553455
Flag management in processors enabled for speculative execution of micro-operation traces Oct 25, 2006 Issued
Array ( [id] => 343150 [patent_doc_number] => 07502911 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-03-10 [patent_title] => 'Variable length instruction fetching that retrieves second instruction in dependence upon first instruction length' [patent_app_type] => utility [patent_app_number] => 11/535005 [patent_app_country] => US [patent_app_date] => 2006-09-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 15165 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 239 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/502/07502911.pdf [firstpage_image] =>[orig_patent_app_number] => 11535005 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/535005
Variable length instruction fetching that retrieves second instruction in dependence upon first instruction length Sep 24, 2006 Issued
Array ( [id] => 4940453 [patent_doc_number] => 20080077772 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-03-27 [patent_title] => 'Method and apparatus for performing select operations' [patent_app_type] => utility [patent_app_number] => 11/526065 [patent_app_country] => US [patent_app_date] => 2006-09-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 12415 [patent_no_of_claims] => 36 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0077/20080077772.pdf [firstpage_image] =>[orig_patent_app_number] => 11526065 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/526065
Method and apparatus for performing select operations Sep 21, 2006 Abandoned
Array ( [id] => 4923701 [patent_doc_number] => 20080072018 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-03-20 [patent_title] => 'DATA PROCESSING SYSTEM, PROCESSOR AND METHOD OF DATA PROCESSING EMPLOYING AN IMPROVED INSTRUCTION DESTINATION TAG' [patent_app_type] => utility [patent_app_number] => 11/533379 [patent_app_country] => US [patent_app_date] => 2006-09-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3610 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0072/20080072018.pdf [firstpage_image] =>[orig_patent_app_number] => 11533379 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/533379
System for managing data dependency using bit field instruction destination vector identifying destination for execution results Sep 19, 2006 Issued
Array ( [id] => 4923700 [patent_doc_number] => 20080072017 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-03-20 [patent_title] => 'Processing System having a Plurality of Processing Units with Program Counters and Related Method for Processing Instructions in the Processing System' [patent_app_type] => utility [patent_app_number] => 11/532918 [patent_app_country] => US [patent_app_date] => 2006-09-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3516 [patent_no_of_claims] => 40 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0072/20080072017.pdf [firstpage_image] =>[orig_patent_app_number] => 11532918 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/532918
Processing System having a Plurality of Processing Units with Program Counters and Related Method for Processing Instructions in the Processing System Sep 18, 2006 Abandoned
Array ( [id] => 366601 [patent_doc_number] => 07484076 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2009-01-27 [patent_title] => 'Executing an SIMD instruction requiring P operations on an execution unit that performs Q operations at a time (Q utility [patent_app_number] => 11/532853 [patent_app_country] => US [patent_app_date] => 2006-09-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 10212 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 175 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/484/07484076.pdf [firstpage_image] =>[orig_patent_app_number] => 11532853 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/532853
Executing an SIMD instruction requiring P operations on an execution unit that performs Q operations at a time (Q Sep 17, 2006 Issued
Array ( [id] => 108231 [patent_doc_number] => 07725894 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-05-25 [patent_title] => 'Enhanced un-privileged computer instruction to store a facility list' [patent_app_type] => utility [patent_app_number] => 11/532177 [patent_app_country] => US [patent_app_date] => 2006-09-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 3718 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 227 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/725/07725894.pdf [firstpage_image] =>[orig_patent_app_number] => 11532177 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/532177
Enhanced un-privileged computer instruction to store a facility list Sep 14, 2006 Issued
Array ( [id] => 5173571 [patent_doc_number] => 20070074010 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-03-29 [patent_title] => 'Processor for processing instruction set of plurality of instructions packed into single code' [patent_app_type] => utility [patent_app_number] => 11/520616 [patent_app_country] => US [patent_app_date] => 2006-09-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 5340 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0074/20070074010.pdf [firstpage_image] =>[orig_patent_app_number] => 11520616 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/520616
Processor for executing instructions containing either single operation or packed plurality of operations dependent upon instruction status indicator Sep 13, 2006 Issued
Array ( [id] => 4923707 [patent_doc_number] => 20080072024 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-03-20 [patent_title] => 'Predicting instruction branches with bimodal, little global, big global, and loop (BgGL) branch predictors' [patent_app_type] => utility [patent_app_number] => 11/521015 [patent_app_country] => US [patent_app_date] => 2006-09-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 7279 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0072/20080072024.pdf [firstpage_image] =>[orig_patent_app_number] => 11521015 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/521015
Predicting instruction branches with bimodal, little global, big global, and loop (BgGL) branch predictors Sep 13, 2006 Abandoned
Array ( [id] => 313139 [patent_doc_number] => 07529917 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-05-05 [patent_title] => 'Method and apparatus for interrupt handling during loop processing in reconfigurable coarse grained array' [patent_app_type] => utility [patent_app_number] => 11/519858 [patent_app_country] => US [patent_app_date] => 2006-09-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 6786 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/529/07529917.pdf [firstpage_image] =>[orig_patent_app_number] => 11519858 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/519858
Method and apparatus for interrupt handling during loop processing in reconfigurable coarse grained array Sep 12, 2006 Issued
Array ( [id] => 839890 [patent_doc_number] => 07395416 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2008-07-01 [patent_title] => 'Computer processing system employing an instruction reorder buffer' [patent_app_type] => utility [patent_app_number] => 11/531042 [patent_app_country] => US [patent_app_date] => 2006-09-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 4860 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/395/07395416.pdf [firstpage_image] =>[orig_patent_app_number] => 11531042 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/531042
Computer processing system employing an instruction reorder buffer Sep 11, 2006 Issued
Array ( [id] => 4862178 [patent_doc_number] => 20080270759 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-10-30 [patent_title] => 'Computer Having Dynamically-Changeable Instruction Set in Real Time' [patent_app_type] => utility [patent_app_number] => 11/884506 [patent_app_country] => US [patent_app_date] => 2006-08-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 3806 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0270/20080270759.pdf [firstpage_image] =>[orig_patent_app_number] => 11884506 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/884506
Computer Having Dynamically-Changeable Instruction Set in Real Time Aug 24, 2006 Abandoned
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