
Do H. Yoo
Examiner (ID: 7566)
| Most Active Art Unit | 2511 |
| Art Unit(s) | 2824, 2818, 2502, 2511 |
| Total Applications | 794 |
| Issued Applications | 686 |
| Pending Applications | 18 |
| Abandoned Applications | 90 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 6609250
[patent_doc_number] => 20100099237
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2010-04-22
[patent_title] => 'FLEXIBLE DISPLAY SUBSTRATES'
[patent_app_type] => utility
[patent_app_number] => 12/643501
[patent_app_country] => US
[patent_app_date] => 2009-12-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 5249
[patent_no_of_claims] => 27
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0099/20100099237.pdf
[firstpage_image] =>[orig_patent_app_number] => 12643501
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/643501 | Flexible display substrates | Dec 20, 2009 | Issued |
Array
(
[id] => 6560477
[patent_doc_number] => 20100059662
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2010-03-11
[patent_title] => 'CMOS IMAGER AND APPARATUS WITH SELECTIVELY SILICIDED GATES'
[patent_app_type] => utility
[patent_app_number] => 12/619282
[patent_app_country] => US
[patent_app_date] => 2009-11-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
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[patent_no_of_claims] => 20
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[patent_maintenance] => 1
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[pdf_file] => publications/A1/0059/20100059662.pdf
[firstpage_image] =>[orig_patent_app_number] => 12619282
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/619282 | CMOS IMAGER AND APPARATUS WITH SELECTIVELY SILICIDED GATES | Nov 15, 2009 | Abandoned |
Array
(
[id] => 6365250
[patent_doc_number] => 20100079645
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2010-04-01
[patent_title] => 'CMOS IMAGER AND SYSTEM WITH SELECTIVELY SILICIDED GATES'
[patent_app_type] => utility
[patent_app_number] => 12/619296
[patent_app_country] => US
[patent_app_date] => 2009-11-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
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[patent_no_of_words] => 7466
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[pdf_file] => publications/A1/0079/20100079645.pdf
[firstpage_image] =>[orig_patent_app_number] => 12619296
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/619296 | CMOS IMAGER AND SYSTEM WITH SELECTIVELY SILICIDED GATES | Nov 15, 2009 | Abandoned |
Array
(
[id] => 4515034
[patent_doc_number] => 07932153
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2011-04-26
[patent_title] => 'Semiconductor device and method for fabricating the same'
[patent_app_type] => utility
[patent_app_number] => 12/605875
[patent_app_country] => US
[patent_app_date] => 2009-10-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
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[patent_no_of_words] => 7032
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/932/07932153.pdf
[firstpage_image] =>[orig_patent_app_number] => 12605875
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/605875 | Semiconductor device and method for fabricating the same | Oct 25, 2009 | Issued |
Array
(
[id] => 6458342
[patent_doc_number] => 20100090331
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2010-04-15
[patent_title] => 'SEMICONDUCTOR DIE PACKAGE INCLUDING MULTIPLE DIES AND A COMMON NODE STRUCTURE'
[patent_app_type] => utility
[patent_app_number] => 12/575641
[patent_app_country] => US
[patent_app_date] => 2009-10-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
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[patent_no_of_words] => 4643
[patent_no_of_claims] => 24
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[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0090/20100090331.pdf
[firstpage_image] =>[orig_patent_app_number] => 12575641
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/575641 | Semiconductor die package including multiple dies and a common node structure | Oct 7, 2009 | Issued |
Array
(
[id] => 6592093
[patent_doc_number] => 20100062243
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2010-03-11
[patent_title] => 'METHOD FOR TREATING SEMICONDUCTOR PROCESSING COMPONENTS AND COMPONENTS FORMED THEREBY'
[patent_app_type] => utility
[patent_app_number] => 12/567969
[patent_app_country] => US
[patent_app_date] => 2009-09-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
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[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0062/20100062243.pdf
[firstpage_image] =>[orig_patent_app_number] => 12567969
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/567969 | METHOD FOR TREATING SEMICONDUCTOR PROCESSING COMPONENTS AND COMPONENTS FORMED THEREBY | Sep 27, 2009 | Abandoned |
Array
(
[id] => 8339178
[patent_doc_number] => 08241101
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2012-08-14
[patent_title] => 'Symbol recognition arrangement'
[patent_app_type] => utility
[patent_app_number] => 12/457027
[patent_app_country] => US
[patent_app_date] => 2009-05-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 3616
[patent_no_of_claims] => 16
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[patent_words_short_claim] => 130
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12457027
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/457027 | Symbol recognition arrangement | May 28, 2009 | Issued |
Array
(
[id] => 6021313
[patent_doc_number] => 20110049639
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2011-03-03
[patent_title] => 'INTEGRATED CIRCUIT MANUFACTURING METHOD AND INTEGRATED CIRCUIT'
[patent_app_type] => utility
[patent_app_number] => 12/989478
[patent_app_country] => US
[patent_app_date] => 2009-04-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
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[patent_no_of_words] => 3973
[patent_no_of_claims] => 15
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[pdf_file] => publications/A1/0049/20110049639.pdf
[firstpage_image] =>[orig_patent_app_number] => 12989478
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/989478 | INTEGRATED CIRCUIT MANUFACTURING METHOD AND INTEGRATED CIRCUIT | Apr 23, 2009 | Abandoned |
Array
(
[id] => 5389140
[patent_doc_number] => 20090206452
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2009-08-20
[patent_title] => 'METHOD AND SYSTEM FOR CREATING SELF-ALIGNED TWIN WELLS WITH CO-PLANAR SURFACES IN A SEMICONDUCTOR DEVICE'
[patent_app_type] => utility
[patent_app_number] => 12/426921
[patent_app_country] => US
[patent_app_date] => 2009-04-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
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[pdf_file] => publications/A1/0206/20090206452.pdf
[firstpage_image] =>[orig_patent_app_number] => 12426921
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/426921 | Method and system for creating self-aligned twin wells with co-planar surfaces in a semiconductor device | Apr 19, 2009 | Issued |
Array
(
[id] => 5367931
[patent_doc_number] => 20090305490
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2009-12-10
[patent_title] => 'METHOD FOR PRODUCING SEMICONDUCTOR DEVICE'
[patent_app_type] => utility
[patent_app_number] => 12/425016
[patent_app_country] => US
[patent_app_date] => 2009-04-16
[patent_effective_date] => 0000-00-00
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[pdf_file] => publications/A1/0305/20090305490.pdf
[firstpage_image] =>[orig_patent_app_number] => 12425016
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/425016 | METHOD FOR PRODUCING SEMICONDUCTOR DEVICE | Apr 15, 2009 | Abandoned |
Array
(
[id] => 5474103
[patent_doc_number] => 20090247269
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2009-10-01
[patent_title] => 'SLOT MACHINE HAVING FEATURE IN SETTING SEQUENCE IN WHICH SYMBOLS ARE REARRANGED ON DEFINED AREAS TO SPECIFIC SEQUENCE PATTERN AND CONTROL METHOD OF THE SLOT MACHINE'
[patent_app_type] => utility
[patent_app_number] => 12/408245
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[patent_app_date] => 2009-03-20
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[pdf_file] => publications/A1/0247/20090247269.pdf
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Array
(
[id] => 5435756
[patent_doc_number] => 20090170343
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2009-07-02
[patent_title] => 'METHOD AND APPARATUS FOR TREATING A SEMI-CONDUCTOR SUBSTRATE'
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[patent_app_number] => 12/402720
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/402720 | METHOD AND APPARATUS FOR TREATING A SEMI-CONDUCTOR SUBSTRATE | Mar 11, 2009 | Abandoned |
Array
(
[id] => 5353047
[patent_doc_number] => 20090184391
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[patent_kind] => A1
[patent_issue_date] => 2009-07-23
[patent_title] => 'Semiconductor devices having fuses and methods of forming the same'
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[patent_app_number] => 12/382168
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Array
(
[id] => 5499230
[patent_doc_number] => 20090159918
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2009-06-25
[patent_title] => 'SEMICONDUCTOR LIGHT EMITTING DEVICES AND SUBMOUNTS AND METHODS FOR FORMING THE SAME'
[patent_app_type] => utility
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/397555 | Methods for forming semiconductor light emitting devices and submounts | Mar 3, 2009 | Issued |
Array
(
[id] => 13664
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[patent_title] => 'Capacitive substrate and method of making same'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/380616 | Capacitive substrate and method of making same | Mar 1, 2009 | Issued |
Array
(
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[patent_title] => 'VOLTAGE-CONTROLLED SEMICONDUCTOR INDUCTOR AND METHOD'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/395254 | Voltage-controlled semiconductor inductor and method | Feb 26, 2009 | Issued |
Array
(
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[patent_title] => 'Method for breaking adhesive film mounted on back of wafer'
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Array
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Array
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[patent_title] => 'Wiring placement method of wirings having different length and semiconductor integrated circuit device'
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Array
(
[id] => 6376785
[patent_doc_number] => 20100081494
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[patent_kind] => A1
[patent_issue_date] => 2010-04-01
[patent_title] => 'GAMING APPARATUS AND METHOD OF PLAYING A GAME WITH A SECONDARY WILD SYMBOL MATRIX'
[patent_app_type] => utility
[patent_app_number] => 12/359311
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/359311 | GAMING APPARATUS AND METHOD OF PLAYING A GAME WITH A SECONDARY WILD SYMBOL MATRIX | Jan 23, 2009 | Abandoned |