Search

Do H. Yoo

Examiner (ID: 7566)

Most Active Art Unit
2511
Art Unit(s)
2824, 2818, 2502, 2511
Total Applications
794
Issued Applications
686
Pending Applications
18
Abandoned Applications
90

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 6609250 [patent_doc_number] => 20100099237 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-04-22 [patent_title] => 'FLEXIBLE DISPLAY SUBSTRATES' [patent_app_type] => utility [patent_app_number] => 12/643501 [patent_app_country] => US [patent_app_date] => 2009-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5249 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0099/20100099237.pdf [firstpage_image] =>[orig_patent_app_number] => 12643501 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/643501
Flexible display substrates Dec 20, 2009 Issued
Array ( [id] => 6560477 [patent_doc_number] => 20100059662 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-03-11 [patent_title] => 'CMOS IMAGER AND APPARATUS WITH SELECTIVELY SILICIDED GATES' [patent_app_type] => utility [patent_app_number] => 12/619282 [patent_app_country] => US [patent_app_date] => 2009-11-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 7467 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0059/20100059662.pdf [firstpage_image] =>[orig_patent_app_number] => 12619282 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/619282
CMOS IMAGER AND APPARATUS WITH SELECTIVELY SILICIDED GATES Nov 15, 2009 Abandoned
Array ( [id] => 6365250 [patent_doc_number] => 20100079645 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-04-01 [patent_title] => 'CMOS IMAGER AND SYSTEM WITH SELECTIVELY SILICIDED GATES' [patent_app_type] => utility [patent_app_number] => 12/619296 [patent_app_country] => US [patent_app_date] => 2009-11-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 7466 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0079/20100079645.pdf [firstpage_image] =>[orig_patent_app_number] => 12619296 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/619296
CMOS IMAGER AND SYSTEM WITH SELECTIVELY SILICIDED GATES Nov 15, 2009 Abandoned
Array ( [id] => 4515034 [patent_doc_number] => 07932153 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-04-26 [patent_title] => 'Semiconductor device and method for fabricating the same' [patent_app_type] => utility [patent_app_number] => 12/605875 [patent_app_country] => US [patent_app_date] => 2009-10-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 15 [patent_no_of_words] => 7032 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 318 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/932/07932153.pdf [firstpage_image] =>[orig_patent_app_number] => 12605875 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/605875
Semiconductor device and method for fabricating the same Oct 25, 2009 Issued
Array ( [id] => 6458342 [patent_doc_number] => 20100090331 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-04-15 [patent_title] => 'SEMICONDUCTOR DIE PACKAGE INCLUDING MULTIPLE DIES AND A COMMON NODE STRUCTURE' [patent_app_type] => utility [patent_app_number] => 12/575641 [patent_app_country] => US [patent_app_date] => 2009-10-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 4643 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0090/20100090331.pdf [firstpage_image] =>[orig_patent_app_number] => 12575641 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/575641
Semiconductor die package including multiple dies and a common node structure Oct 7, 2009 Issued
Array ( [id] => 6592093 [patent_doc_number] => 20100062243 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-03-11 [patent_title] => 'METHOD FOR TREATING SEMICONDUCTOR PROCESSING COMPONENTS AND COMPONENTS FORMED THEREBY' [patent_app_type] => utility [patent_app_number] => 12/567969 [patent_app_country] => US [patent_app_date] => 2009-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 6190 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0062/20100062243.pdf [firstpage_image] =>[orig_patent_app_number] => 12567969 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/567969
METHOD FOR TREATING SEMICONDUCTOR PROCESSING COMPONENTS AND COMPONENTS FORMED THEREBY Sep 27, 2009 Abandoned
Array ( [id] => 8339178 [patent_doc_number] => 08241101 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-08-14 [patent_title] => 'Symbol recognition arrangement' [patent_app_type] => utility [patent_app_number] => 12/457027 [patent_app_country] => US [patent_app_date] => 2009-05-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3616 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12457027 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/457027
Symbol recognition arrangement May 28, 2009 Issued
Array ( [id] => 6021313 [patent_doc_number] => 20110049639 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-03-03 [patent_title] => 'INTEGRATED CIRCUIT MANUFACTURING METHOD AND INTEGRATED CIRCUIT' [patent_app_type] => utility [patent_app_number] => 12/989478 [patent_app_country] => US [patent_app_date] => 2009-04-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3973 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0049/20110049639.pdf [firstpage_image] =>[orig_patent_app_number] => 12989478 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/989478
INTEGRATED CIRCUIT MANUFACTURING METHOD AND INTEGRATED CIRCUIT Apr 23, 2009 Abandoned
Array ( [id] => 5389140 [patent_doc_number] => 20090206452 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-08-20 [patent_title] => 'METHOD AND SYSTEM FOR CREATING SELF-ALIGNED TWIN WELLS WITH CO-PLANAR SURFACES IN A SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 12/426921 [patent_app_country] => US [patent_app_date] => 2009-04-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 4319 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0206/20090206452.pdf [firstpage_image] =>[orig_patent_app_number] => 12426921 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/426921
Method and system for creating self-aligned twin wells with co-planar surfaces in a semiconductor device Apr 19, 2009 Issued
Array ( [id] => 5367931 [patent_doc_number] => 20090305490 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-12-10 [patent_title] => 'METHOD FOR PRODUCING SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 12/425016 [patent_app_country] => US [patent_app_date] => 2009-04-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 26 [patent_no_of_words] => 19519 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0305/20090305490.pdf [firstpage_image] =>[orig_patent_app_number] => 12425016 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/425016
METHOD FOR PRODUCING SEMICONDUCTOR DEVICE Apr 15, 2009 Abandoned
Array ( [id] => 5474103 [patent_doc_number] => 20090247269 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-10-01 [patent_title] => 'SLOT MACHINE HAVING FEATURE IN SETTING SEQUENCE IN WHICH SYMBOLS ARE REARRANGED ON DEFINED AREAS TO SPECIFIC SEQUENCE PATTERN AND CONTROL METHOD OF THE SLOT MACHINE' [patent_app_type] => utility [patent_app_number] => 12/408245 [patent_app_country] => US [patent_app_date] => 2009-03-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 11704 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0247/20090247269.pdf [firstpage_image] =>[orig_patent_app_number] => 12408245 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/408245
SLOT MACHINE HAVING FEATURE IN SETTING SEQUENCE IN WHICH SYMBOLS ARE REARRANGED ON DEFINED AREAS TO SPECIFIC SEQUENCE PATTERN AND CONTROL METHOD OF THE SLOT MACHINE Mar 19, 2009 Abandoned
Array ( [id] => 5435756 [patent_doc_number] => 20090170343 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-07-02 [patent_title] => 'METHOD AND APPARATUS FOR TREATING A SEMI-CONDUCTOR SUBSTRATE' [patent_app_type] => utility [patent_app_number] => 12/402720 [patent_app_country] => US [patent_app_date] => 2009-03-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 2850 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0170/20090170343.pdf [firstpage_image] =>[orig_patent_app_number] => 12402720 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/402720
METHOD AND APPARATUS FOR TREATING A SEMI-CONDUCTOR SUBSTRATE Mar 11, 2009 Abandoned
Array ( [id] => 5353047 [patent_doc_number] => 20090184391 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-07-23 [patent_title] => 'Semiconductor devices having fuses and methods of forming the same' [patent_app_type] => utility [patent_app_number] => 12/382168 [patent_app_country] => US [patent_app_date] => 2009-03-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 9051 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0184/20090184391.pdf [firstpage_image] =>[orig_patent_app_number] => 12382168 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/382168
Semiconductor devices having fuses and methods of forming the same Mar 9, 2009 Abandoned
Array ( [id] => 5499230 [patent_doc_number] => 20090159918 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-06-25 [patent_title] => 'SEMICONDUCTOR LIGHT EMITTING DEVICES AND SUBMOUNTS AND METHODS FOR FORMING THE SAME' [patent_app_type] => utility [patent_app_number] => 12/397555 [patent_app_country] => US [patent_app_date] => 2009-03-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 6433 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0159/20090159918.pdf [firstpage_image] =>[orig_patent_app_number] => 12397555 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/397555
Methods for forming semiconductor light emitting devices and submounts Mar 3, 2009 Issued
Array ( [id] => 13664 [patent_doc_number] => 07803688 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-09-28 [patent_title] => 'Capacitive substrate and method of making same' [patent_app_type] => utility [patent_app_number] => 12/380616 [patent_app_country] => US [patent_app_date] => 2009-03-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 7 [patent_no_of_words] => 11693 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/803/07803688.pdf [firstpage_image] =>[orig_patent_app_number] => 12380616 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/380616
Capacitive substrate and method of making same Mar 1, 2009 Issued
Array ( [id] => 5377841 [patent_doc_number] => 20090189680 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-07-30 [patent_title] => 'VOLTAGE-CONTROLLED SEMICONDUCTOR INDUCTOR AND METHOD' [patent_app_type] => utility [patent_app_number] => 12/395254 [patent_app_country] => US [patent_app_date] => 2009-02-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4881 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0189/20090189680.pdf [firstpage_image] =>[orig_patent_app_number] => 12395254 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/395254
Voltage-controlled semiconductor inductor and method Feb 26, 2009 Issued
Array ( [id] => 132534 [patent_doc_number] => 07696014 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-04-13 [patent_title] => 'Method for breaking adhesive film mounted on back of wafer' [patent_app_type] => utility [patent_app_number] => 12/390024 [patent_app_country] => US [patent_app_date] => 2009-02-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 8998 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 163 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/696/07696014.pdf [firstpage_image] =>[orig_patent_app_number] => 12390024 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/390024
Method for breaking adhesive film mounted on back of wafer Feb 19, 2009 Issued
Array ( [id] => 7724660 [patent_doc_number] => 08097932 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-01-17 [patent_title] => 'Ultra low κ plasma enhanced chemical vapor deposition processes using a single bifunctional precursor containing both a SiCOH matrix functionality and organic porogen functionality' [patent_app_type] => utility [patent_app_number] => 12/371180 [patent_app_country] => US [patent_app_date] => 2009-02-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 8025 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/097/08097932.pdf [firstpage_image] =>[orig_patent_app_number] => 12371180 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/371180
Ultra low κ plasma enhanced chemical vapor deposition processes using a single bifunctional precursor containing both a SiCOH matrix functionality and organic porogen functionality Feb 12, 2009 Issued
Array ( [id] => 7998071 [patent_doc_number] => 08080883 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-12-20 [patent_title] => 'Wiring placement method of wirings having different length and semiconductor integrated circuit device' [patent_app_type] => utility [patent_app_number] => 12/320784 [patent_app_country] => US [patent_app_date] => 2009-02-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 20 [patent_no_of_words] => 3488 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 233 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/080/08080883.pdf [firstpage_image] =>[orig_patent_app_number] => 12320784 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/320784
Wiring placement method of wirings having different length and semiconductor integrated circuit device Feb 3, 2009 Issued
Array ( [id] => 6376785 [patent_doc_number] => 20100081494 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-04-01 [patent_title] => 'GAMING APPARATUS AND METHOD OF PLAYING A GAME WITH A SECONDARY WILD SYMBOL MATRIX' [patent_app_type] => utility [patent_app_number] => 12/359311 [patent_app_country] => US [patent_app_date] => 2009-01-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4115 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0081/20100081494.pdf [firstpage_image] =>[orig_patent_app_number] => 12359311 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/359311
GAMING APPARATUS AND METHOD OF PLAYING A GAME WITH A SECONDARY WILD SYMBOL MATRIX Jan 23, 2009 Abandoned
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