Search

Do H. Yoo

Examiner (ID: 7566)

Most Active Art Unit
2511
Art Unit(s)
2824, 2818, 2502, 2511
Total Applications
794
Issued Applications
686
Pending Applications
18
Abandoned Applications
90

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 3882727 [patent_doc_number] => 05838604 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-11-17 [patent_title] => 'Semiconductor memory device with an increased band width' [patent_app_type] => 1 [patent_app_number] => 8/803448 [patent_app_country] => US [patent_app_date] => 1997-02-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 60 [patent_no_of_words] => 9848 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/838/05838604.pdf [firstpage_image] =>[orig_patent_app_number] => 803448 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/803448
Semiconductor memory device with an increased band width Feb 19, 1997 Issued
Array ( [id] => 3809435 [patent_doc_number] => 05828616 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-10-27 [patent_title] => 'Sensing scheme for flash memory with multilevel cells' [patent_app_type] => 1 [patent_app_number] => 8/801004 [patent_app_country] => US [patent_app_date] => 1997-02-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5823 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 192 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/828/05828616.pdf [firstpage_image] =>[orig_patent_app_number] => 801004 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/801004
Sensing scheme for flash memory with multilevel cells Feb 18, 1997 Issued
Array ( [id] => 3899024 [patent_doc_number] => 05724302 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-03-03 [patent_title] => 'High density decoder' [patent_app_type] => 1 [patent_app_number] => 8/801252 [patent_app_country] => US [patent_app_date] => 1997-02-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 3686 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 155 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/724/05724302.pdf [firstpage_image] =>[orig_patent_app_number] => 801252 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/801252
High density decoder Feb 18, 1997 Issued
Array ( [id] => 3913068 [patent_doc_number] => 05751647 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-05-12 [patent_title] => 'On-chip memory redundancy circuitry for programmable non-volatile memories, and methods for programming same' [patent_app_type] => 1 [patent_app_number] => 8/802376 [patent_app_country] => US [patent_app_date] => 1997-02-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 5161 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/751/05751647.pdf [firstpage_image] =>[orig_patent_app_number] => 802376 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/802376
On-chip memory redundancy circuitry for programmable non-volatile memories, and methods for programming same Feb 18, 1997 Issued
Array ( [id] => 3853609 [patent_doc_number] => 05745401 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-04-28 [patent_title] => 'High-speed programmable read only memory' [patent_app_type] => 1 [patent_app_number] => 8/800346 [patent_app_country] => US [patent_app_date] => 1997-02-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 12 [patent_no_of_words] => 3355 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 55 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/745/05745401.pdf [firstpage_image] =>[orig_patent_app_number] => 800346 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/800346
High-speed programmable read only memory Feb 13, 1997 Issued
Array ( [id] => 4144551 [patent_doc_number] => 06034908 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-03-07 [patent_title] => 'Sense amplifying methods and sense amplification integrated devices' [patent_app_type] => 1 [patent_app_number] => 8/797347 [patent_app_country] => US [patent_app_date] => 1997-02-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 11 [patent_no_of_words] => 7160 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/034/06034908.pdf [firstpage_image] =>[orig_patent_app_number] => 797347 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/797347
Sense amplifying methods and sense amplification integrated devices Feb 10, 1997 Issued
Array ( [id] => 3892106 [patent_doc_number] => 05805502 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-09-08 [patent_title] => 'System for constant field erasure in a FLASH EPROM' [patent_app_type] => 1 [patent_app_number] => 8/795024 [patent_app_country] => US [patent_app_date] => 1997-02-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 2121 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 56 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/805/05805502.pdf [firstpage_image] =>[orig_patent_app_number] => 795024 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/795024
System for constant field erasure in a FLASH EPROM Feb 3, 1997 Issued
Array ( [id] => 4015086 [patent_doc_number] => 05859795 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-01-12 [patent_title] => 'Multi-level memory circuits and corresponding reading and writing methods' [patent_app_type] => 1 [patent_app_number] => 8/791348 [patent_app_country] => US [patent_app_date] => 1997-01-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 17 [patent_no_of_words] => 5761 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/859/05859795.pdf [firstpage_image] =>[orig_patent_app_number] => 791348 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/791348
Multi-level memory circuits and corresponding reading and writing methods Jan 29, 1997 Issued
Array ( [id] => 3816128 [patent_doc_number] => 05854770 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-12-29 [patent_title] => 'Decoding hierarchical architecture for high integration memories' [patent_app_type] => 1 [patent_app_number] => 8/791746 [patent_app_country] => US [patent_app_date] => 1997-01-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 23 [patent_no_of_words] => 4348 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 232 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/854/05854770.pdf [firstpage_image] =>[orig_patent_app_number] => 791746 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/791746
Decoding hierarchical architecture for high integration memories Jan 29, 1997 Issued
Array ( [id] => 4034691 [patent_doc_number] => 05926433 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-07-20 [patent_title] => 'Dual strobed negative pumped worldlines for dynamic random access memories' [patent_app_type] => 1 [patent_app_number] => 8/806703 [patent_app_country] => US [patent_app_date] => 1997-01-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 2958 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/926/05926433.pdf [firstpage_image] =>[orig_patent_app_number] => 806703 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/806703
Dual strobed negative pumped worldlines for dynamic random access memories Jan 28, 1997 Issued
Array ( [id] => 3790103 [patent_doc_number] => 05757705 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-05-26 [patent_title] => 'SDRAM clocking test mode' [patent_app_type] => 1 [patent_app_number] => 8/787149 [patent_app_country] => US [patent_app_date] => 1997-01-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 4320 [patent_no_of_claims] => 39 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/757/05757705.pdf [firstpage_image] =>[orig_patent_app_number] => 787149 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/787149
SDRAM clocking test mode Jan 21, 1997 Issued
Array ( [id] => 3716029 [patent_doc_number] => 05654933 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-08-05 [patent_title] => 'Equilibrated sam read transfer circuit' [patent_app_type] => 1 [patent_app_number] => 8/785801 [patent_app_country] => US [patent_app_date] => 1997-01-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4736 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 188 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/654/05654933.pdf [firstpage_image] =>[orig_patent_app_number] => 785801 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/785801
Equilibrated sam read transfer circuit Jan 20, 1997 Issued
Array ( [id] => 3809252 [patent_doc_number] => 05828604 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-10-27 [patent_title] => 'Non-volatile semiconductor memory device having large margin of readout operation for variation in external power supply voltage' [patent_app_type] => 1 [patent_app_number] => 8/781247 [patent_app_country] => US [patent_app_date] => 1997-01-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 20 [patent_no_of_words] => 11327 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 227 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/828/05828604.pdf [firstpage_image] =>[orig_patent_app_number] => 781247 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/781247
Non-volatile semiconductor memory device having large margin of readout operation for variation in external power supply voltage Jan 9, 1997 Issued
Array ( [id] => 3844674 [patent_doc_number] => 05761137 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-06-02 [patent_title] => 'DRAM access system and method' [patent_app_type] => 1 [patent_app_number] => 8/782561 [patent_app_country] => US [patent_app_date] => 1997-01-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3408 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/761/05761137.pdf [firstpage_image] =>[orig_patent_app_number] => 782561 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/782561
DRAM access system and method Jan 8, 1997 Issued
Array ( [id] => 3892185 [patent_doc_number] => 05805508 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-09-08 [patent_title] => 'Semiconductor memory device with reduced leak current' [patent_app_type] => 1 [patent_app_number] => 8/780247 [patent_app_country] => US [patent_app_date] => 1997-01-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 45 [patent_no_of_words] => 28985 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/805/05805508.pdf [firstpage_image] =>[orig_patent_app_number] => 780247 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/780247
Semiconductor memory device with reduced leak current Jan 7, 1997 Issued
Array ( [id] => 4054526 [patent_doc_number] => 05909405 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-06-01 [patent_title] => 'Nonvolatile semiconductor memory' [patent_app_type] => 1 [patent_app_number] => 8/774646 [patent_app_country] => US [patent_app_date] => 1996-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5463 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 311 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/909/05909405.pdf [firstpage_image] =>[orig_patent_app_number] => 774646 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/774646
Nonvolatile semiconductor memory Dec 29, 1996 Issued
Array ( [id] => 3898892 [patent_doc_number] => 05724294 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-03-03 [patent_title] => 'Self-tracking sense amplifier strobing circuit and method' [patent_app_type] => 1 [patent_app_number] => 8/777546 [patent_app_country] => US [patent_app_date] => 1996-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4218 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/724/05724294.pdf [firstpage_image] =>[orig_patent_app_number] => 777546 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/777546
Self-tracking sense amplifier strobing circuit and method Dec 29, 1996 Issued
Array ( [id] => 3892366 [patent_doc_number] => 05805521 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-09-08 [patent_title] => 'DRAM memory system' [patent_app_type] => 1 [patent_app_number] => 8/773150 [patent_app_country] => US [patent_app_date] => 1996-12-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 5191 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 227 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/805/05805521.pdf [firstpage_image] =>[orig_patent_app_number] => 773150 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/773150
DRAM memory system Dec 25, 1996 Issued
Array ( [id] => 3772282 [patent_doc_number] => 05742539 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-04-21 [patent_title] => 'Integrated circuit for content addressable memory' [patent_app_type] => 1 [patent_app_number] => 8/767294 [patent_app_country] => US [patent_app_date] => 1996-12-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 5280 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 175 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/742/05742539.pdf [firstpage_image] =>[orig_patent_app_number] => 767294 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/767294
Integrated circuit for content addressable memory Dec 15, 1996 Issued
Array ( [id] => 3873347 [patent_doc_number] => 05796663 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-08-18 [patent_title] => 'Address signal storage circuit of data repair controller' [patent_app_type] => 1 [patent_app_number] => 8/764444 [patent_app_country] => US [patent_app_date] => 1996-12-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 6721 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 155 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/796/05796663.pdf [firstpage_image] =>[orig_patent_app_number] => 764444 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/764444
Address signal storage circuit of data repair controller Dec 11, 1996 Issued
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