Search

Dominic E. Rego

Examiner (ID: 392, Phone: (571)272-8132 , Office: P/2647 )

Most Active Art Unit
2647
Art Unit(s)
2648, 2618, 2647, 2684
Total Applications
1492
Issued Applications
1279
Pending Applications
77
Abandoned Applications
158

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4572725 [patent_doc_number] => 07847613 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2010-12-07 [patent_title] => 'Variable transconductance mixer system' [patent_app_type] => utility [patent_app_number] => 12/204310 [patent_app_country] => US [patent_app_date] => 2008-09-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 3462 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 215 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/847/07847613.pdf [firstpage_image] =>[orig_patent_app_number] => 12204310 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/204310
Variable transconductance mixer system Sep 3, 2008 Issued
Array ( [id] => 5320505 [patent_doc_number] => 20090058495 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-03-05 [patent_title] => 'CIRCUIT ARRANGEMENT FOR SIGNAL MIXING' [patent_app_type] => utility [patent_app_number] => 12/200262 [patent_app_country] => US [patent_app_date] => 2008-08-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4026 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0058/20090058495.pdf [firstpage_image] =>[orig_patent_app_number] => 12200262 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/200262
Circuit arrangement for signal mixing Aug 27, 2008 Issued
Array ( [id] => 5439741 [patent_doc_number] => 20090091380 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-04-09 [patent_title] => 'DIFFERENTIAL VARACTOR USING GATED VARACTOR' [patent_app_type] => utility [patent_app_number] => 12/195223 [patent_app_country] => US [patent_app_date] => 2008-08-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3082 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0091/20090091380.pdf [firstpage_image] =>[orig_patent_app_number] => 12195223 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/195223
DIFFERENTIAL VARACTOR USING GATED VARACTOR Aug 19, 2008 Abandoned
Array ( [id] => 5341025 [patent_doc_number] => 20090179675 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-07-16 [patent_title] => 'DLL CIRCUIT AND METHOD OF CONTROLLING THE SAME' [patent_app_type] => utility [patent_app_number] => 12/173728 [patent_app_country] => US [patent_app_date] => 2008-07-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4034 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0179/20090179675.pdf [firstpage_image] =>[orig_patent_app_number] => 12173728 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/173728
DLL circuit and method of controlling the same Jul 14, 2008 Issued
Array ( [id] => 5420253 [patent_doc_number] => 20090146708 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-06-11 [patent_title] => 'DLL CIRCUIT AND METHOD OF CONTROLLING THE SAME' [patent_app_type] => utility [patent_app_number] => 12/172137 [patent_app_country] => US [patent_app_date] => 2008-07-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 7205 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0146/20090146708.pdf [firstpage_image] =>[orig_patent_app_number] => 12172137 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/172137
DLL circuit and method of controlling the same Jul 10, 2008 Issued
Array ( [id] => 4451793 [patent_doc_number] => 07965118 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-06-21 [patent_title] => 'Method and apparatus for achieving 50% duty cycle on the output VCO of a phased locked loop' [patent_app_type] => utility [patent_app_number] => 12/171805 [patent_app_country] => US [patent_app_date] => 2008-07-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4191 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 168 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/965/07965118.pdf [firstpage_image] =>[orig_patent_app_number] => 12171805 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/171805
Method and apparatus for achieving 50% duty cycle on the output VCO of a phased locked loop Jul 10, 2008 Issued
Array ( [id] => 5470507 [patent_doc_number] => 20090243673 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-10-01 [patent_title] => 'PHASE LOCKED LOOP SYSTEM AND PHASE-LOCKING METHOD FOR PHASE LOCKED LOOP' [patent_app_type] => utility [patent_app_number] => 12/171302 [patent_app_country] => US [patent_app_date] => 2008-07-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3898 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0243/20090243673.pdf [firstpage_image] =>[orig_patent_app_number] => 12171302 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/171302
PHASE LOCKED LOOP SYSTEM AND PHASE-LOCKING METHOD FOR PHASE LOCKED LOOP Jul 10, 2008 Abandoned
Array ( [id] => 4789961 [patent_doc_number] => 20080290934 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-11-27 [patent_title] => 'REFERENCE BUFFER CIRCUITS' [patent_app_type] => utility [patent_app_number] => 12/169977 [patent_app_country] => US [patent_app_date] => 2008-07-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 6712 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0290/20080290934.pdf [firstpage_image] =>[orig_patent_app_number] => 12169977 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/169977
Reference buffer circuits Jul 8, 2008 Issued
Array ( [id] => 5562082 [patent_doc_number] => 20090134934 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-05-28 [patent_title] => 'ELECTRONIC DEVICE' [patent_app_type] => utility [patent_app_number] => 12/168882 [patent_app_country] => US [patent_app_date] => 2008-07-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 1184 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0134/20090134934.pdf [firstpage_image] =>[orig_patent_app_number] => 12168882 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/168882
ELECTRONIC DEVICE Jul 6, 2008 Abandoned
Array ( [id] => 6595484 [patent_doc_number] => 20100001709 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-01-07 [patent_title] => 'SYSTEM TO GENERATE A REFERENCE FOR A CHARGE PUMP AND ASSOCIATED METHODS' [patent_app_type] => utility [patent_app_number] => 12/168133 [patent_app_country] => US [patent_app_date] => 2008-07-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 3077 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0001/20100001709.pdf [firstpage_image] =>[orig_patent_app_number] => 12168133 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/168133
SYSTEM TO GENERATE A REFERENCE FOR A CHARGE PUMP AND ASSOCIATED METHODS Jul 5, 2008 Abandoned
Array ( [id] => 93546 [patent_doc_number] => 07733129 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-06-08 [patent_title] => 'Method and circuit for generating memory clock signal' [patent_app_type] => utility [patent_app_number] => 12/167797 [patent_app_country] => US [patent_app_date] => 2008-07-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 3039 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/733/07733129.pdf [firstpage_image] =>[orig_patent_app_number] => 12167797 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/167797
Method and circuit for generating memory clock signal Jul 2, 2008 Issued
Array ( [id] => 5499854 [patent_doc_number] => 20090160542 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-06-25 [patent_title] => 'STABLE VOLTAGE GENERATING CIRCUIT FOR A DELAY LOCKED LOOP AND SEMICONDUCTOR MEMORY DEVICE INCLUDING THE SAME AND METHOD OF GENERATING A STABLE VOLTAGE FOR A DELAY LOCKED LOOP' [patent_app_type] => utility [patent_app_number] => 12/166412 [patent_app_country] => US [patent_app_date] => 2008-07-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5938 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0160/20090160542.pdf [firstpage_image] =>[orig_patent_app_number] => 12166412 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/166412
STABLE VOLTAGE GENERATING CIRCUIT FOR A DELAY LOCKED LOOP AND SEMICONDUCTOR MEMORY DEVICE INCLUDING THE SAME AND METHOD OF GENERATING A STABLE VOLTAGE FOR A DELAY LOCKED LOOP Jul 1, 2008 Abandoned
Array ( [id] => 113199 [patent_doc_number] => 07719342 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-05-18 [patent_title] => 'Input latch circuit having fuses for adjusting a setup and hold time' [patent_app_type] => utility [patent_app_number] => 12/164271 [patent_app_country] => US [patent_app_date] => 2008-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 4006 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 198 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/719/07719342.pdf [firstpage_image] =>[orig_patent_app_number] => 12164271 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/164271
Input latch circuit having fuses for adjusting a setup and hold time Jun 29, 2008 Issued
Array ( [id] => 133132 [patent_doc_number] => 07701267 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-04-20 [patent_title] => 'Semiconductor device including phase detector' [patent_app_type] => utility [patent_app_number] => 12/164758 [patent_app_country] => US [patent_app_date] => 2008-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 8563 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/701/07701267.pdf [firstpage_image] =>[orig_patent_app_number] => 12164758 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/164758
Semiconductor device including phase detector Jun 29, 2008 Issued
Array ( [id] => 44044 [patent_doc_number] => 07782107 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-08-24 [patent_title] => 'Method and apparatus for an event tolerant storage circuit' [patent_app_type] => utility [patent_app_number] => 12/165578 [patent_app_country] => US [patent_app_date] => 2008-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 6275 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 184 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/782/07782107.pdf [firstpage_image] =>[orig_patent_app_number] => 12165578 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/165578
Method and apparatus for an event tolerant storage circuit Jun 29, 2008 Issued
Array ( [id] => 4528580 [patent_doc_number] => 07952418 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-05-31 [patent_title] => 'Enhanced transistor gate drive' [patent_app_type] => utility [patent_app_number] => 12/163072 [patent_app_country] => US [patent_app_date] => 2008-06-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 1661 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 175 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/952/07952418.pdf [firstpage_image] =>[orig_patent_app_number] => 12163072 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/163072
Enhanced transistor gate drive Jun 26, 2008 Issued
Array ( [id] => 5346694 [patent_doc_number] => 20090002055 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-01-01 [patent_title] => 'SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 12/146863 [patent_app_country] => US [patent_app_date] => 2008-06-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5476 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0002/20090002055.pdf [firstpage_image] =>[orig_patent_app_number] => 12146863 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/146863
Semiconductor device Jun 25, 2008 Issued
Array ( [id] => 163598 [patent_doc_number] => 07671638 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-03-02 [patent_title] => 'Negative N-epi biasing sensing and high side gate driver output spurious turn-on prevention due to N-epi P-sub diode conduction during N-epi negative transient voltage' [patent_app_type] => utility [patent_app_number] => 12/146736 [patent_app_country] => US [patent_app_date] => 2008-06-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 2098 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 252 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/671/07671638.pdf [firstpage_image] =>[orig_patent_app_number] => 12146736 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/146736
Negative N-epi biasing sensing and high side gate driver output spurious turn-on prevention due to N-epi P-sub diode conduction during N-epi negative transient voltage Jun 25, 2008 Issued
Array ( [id] => 5432783 [patent_doc_number] => 20090167369 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-07-02 [patent_title] => 'LVDS OUTPUT DRIVER' [patent_app_type] => utility [patent_app_number] => 12/146723 [patent_app_country] => US [patent_app_date] => 2008-06-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2045 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0167/20090167369.pdf [firstpage_image] =>[orig_patent_app_number] => 12146723 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/146723
LVDS OUTPUT DRIVER Jun 25, 2008 Abandoned
Array ( [id] => 5346693 [patent_doc_number] => 20090002054 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-01-01 [patent_title] => 'GATE DRIVE APPARATUS' [patent_app_type] => utility [patent_app_number] => 12/144871 [patent_app_country] => US [patent_app_date] => 2008-06-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 11206 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0002/20090002054.pdf [firstpage_image] =>[orig_patent_app_number] => 12144871 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/144871
Gate drive apparatus Jun 23, 2008 Issued
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