
Dominic E. Rego
Examiner (ID: 392, Phone: (571)272-8132 , Office: P/2647 )
| Most Active Art Unit | 2647 |
| Art Unit(s) | 2648, 2618, 2647, 2684 |
| Total Applications | 1492 |
| Issued Applications | 1279 |
| Pending Applications | 77 |
| Abandoned Applications | 158 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 4572725
[patent_doc_number] => 07847613
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2010-12-07
[patent_title] => 'Variable transconductance mixer system'
[patent_app_type] => utility
[patent_app_number] => 12/204310
[patent_app_country] => US
[patent_app_date] => 2008-09-04
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[pdf_file] => patents/07/847/07847613.pdf
[firstpage_image] =>[orig_patent_app_number] => 12204310
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/204310 | Variable transconductance mixer system | Sep 3, 2008 | Issued |
Array
(
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[patent_doc_number] => 20090058495
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2009-03-05
[patent_title] => 'CIRCUIT ARRANGEMENT FOR SIGNAL MIXING'
[patent_app_type] => utility
[patent_app_number] => 12/200262
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/200262 | Circuit arrangement for signal mixing | Aug 27, 2008 | Issued |
Array
(
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[patent_doc_number] => 20090091380
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[patent_title] => 'DIFFERENTIAL VARACTOR USING GATED VARACTOR'
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[patent_app_date] => 2008-08-20
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/195223 | DIFFERENTIAL VARACTOR USING GATED VARACTOR | Aug 19, 2008 | Abandoned |
Array
(
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[patent_title] => 'DLL CIRCUIT AND METHOD OF CONTROLLING THE SAME'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/173728 | DLL circuit and method of controlling the same | Jul 14, 2008 | Issued |
Array
(
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Array
(
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[patent_issue_date] => 2011-06-21
[patent_title] => 'Method and apparatus for achieving 50% duty cycle on the output VCO of a phased locked loop'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/171805 | Method and apparatus for achieving 50% duty cycle on the output VCO of a phased locked loop | Jul 10, 2008 | Issued |
Array
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[id] => 5470507
[patent_doc_number] => 20090243673
[patent_country] => US
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[patent_issue_date] => 2009-10-01
[patent_title] => 'PHASE LOCKED LOOP SYSTEM AND PHASE-LOCKING METHOD FOR PHASE LOCKED LOOP'
[patent_app_type] => utility
[patent_app_number] => 12/171302
[patent_app_country] => US
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[pdf_file] => publications/A1/0243/20090243673.pdf
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/171302 | PHASE LOCKED LOOP SYSTEM AND PHASE-LOCKING METHOD FOR PHASE LOCKED LOOP | Jul 10, 2008 | Abandoned |
Array
(
[id] => 4789961
[patent_doc_number] => 20080290934
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-11-27
[patent_title] => 'REFERENCE BUFFER CIRCUITS'
[patent_app_type] => utility
[patent_app_number] => 12/169977
[patent_app_country] => US
[patent_app_date] => 2008-07-09
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[firstpage_image] =>[orig_patent_app_number] => 12169977
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/169977 | Reference buffer circuits | Jul 8, 2008 | Issued |
Array
(
[id] => 5562082
[patent_doc_number] => 20090134934
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[patent_issue_date] => 2009-05-28
[patent_title] => 'ELECTRONIC DEVICE'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/168882 | ELECTRONIC DEVICE | Jul 6, 2008 | Abandoned |
Array
(
[id] => 6595484
[patent_doc_number] => 20100001709
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[patent_issue_date] => 2010-01-07
[patent_title] => 'SYSTEM TO GENERATE A REFERENCE FOR A CHARGE PUMP AND ASSOCIATED METHODS'
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[patent_app_number] => 12/168133
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/168133 | SYSTEM TO GENERATE A REFERENCE FOR A CHARGE PUMP AND ASSOCIATED METHODS | Jul 5, 2008 | Abandoned |
Array
(
[id] => 93546
[patent_doc_number] => 07733129
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[patent_issue_date] => 2010-06-08
[patent_title] => 'Method and circuit for generating memory clock signal'
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[patent_app_number] => 12/167797
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/167797 | Method and circuit for generating memory clock signal | Jul 2, 2008 | Issued |
Array
(
[id] => 5499854
[patent_doc_number] => 20090160542
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[patent_title] => 'STABLE VOLTAGE GENERATING CIRCUIT FOR A DELAY LOCKED LOOP AND SEMICONDUCTOR MEMORY DEVICE INCLUDING THE SAME AND METHOD OF GENERATING A STABLE VOLTAGE FOR A DELAY LOCKED LOOP'
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Array
(
[id] => 113199
[patent_doc_number] => 07719342
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[patent_issue_date] => 2010-05-18
[patent_title] => 'Input latch circuit having fuses for adjusting a setup and hold time'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/164271 | Input latch circuit having fuses for adjusting a setup and hold time | Jun 29, 2008 | Issued |
Array
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[patent_title] => 'Semiconductor device including phase detector'
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Array
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Array
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[id] => 4528580
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Array
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Array
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Array
(
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Array
(
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[patent_title] => 'GATE DRIVE APPARATUS'
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