Search

Dominick L. Plakkoottam

Examiner (ID: 412, Phone: (571)270-7571 , Office: P/3746 )

Most Active Art Unit
3746
Art Unit(s)
3746
Total Applications
867
Issued Applications
610
Pending Applications
81
Abandoned Applications
195

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 9809751 [patent_doc_number] => 20150021696 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-01-22 [patent_title] => 'MOS Devices Having Epitaxy Regions with Reduced Facets' [patent_app_type] => utility [patent_app_number] => 13/944053 [patent_app_country] => US [patent_app_date] => 2013-07-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 3697 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13944053 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/944053
MOS devices having epitaxy regions with reduced facets Jul 16, 2013 Issued
Array ( [id] => 9809750 [patent_doc_number] => 20150021694 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-01-22 [patent_title] => 'INTEGRATED CIRCUITS HAVING REPLACEMENT METAL GATES WITH IMPROVED THRESHOLD VOLTAGE PERFORMANCE AND METHODS FOR FABRICATING THE SAME' [patent_app_type] => utility [patent_app_number] => 13/943944 [patent_app_country] => US [patent_app_date] => 2013-07-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4161 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13943944 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/943944
Integrated circuits having replacement metal gates with improved threshold voltage performance and methods for fabricating the same Jul 16, 2013 Issued
Array ( [id] => 9393911 [patent_doc_number] => 20140091317 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-04-03 [patent_title] => 'METHOD OF MANUFACTURING SEMICONDUCTOR CRYSTAL SUBSTRATE, METHOD OF MANUFACTURING SEMICONDUCTOR APPARATUS, SEMICONDUCTOR CRYSTAL SUBSTRATE, AND SEMICONDUCTOR APPARATUS' [patent_app_type] => utility [patent_app_number] => 13/943891 [patent_app_country] => US [patent_app_date] => 2013-07-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 4254 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13943891 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/943891
METHOD OF MANUFACTURING SEMICONDUCTOR CRYSTAL SUBSTRATE, METHOD OF MANUFACTURING SEMICONDUCTOR APPARATUS, SEMICONDUCTOR CRYSTAL SUBSTRATE, AND SEMICONDUCTOR APPARATUS Jul 16, 2013 Abandoned
Array ( [id] => 11214954 [patent_doc_number] => 09443996 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-09-13 [patent_title] => 'Dielectric structure for color filter array' [patent_app_type] => utility [patent_app_number] => 13/943907 [patent_app_country] => US [patent_app_date] => 2013-07-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 9 [patent_no_of_words] => 2834 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 164 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13943907 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/943907
Dielectric structure for color filter array Jul 16, 2013 Issued
Array ( [id] => 13019667 [patent_doc_number] => 10032953 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-07-24 [patent_title] => Thin film transistor array substrate and method for manufacturing the same [patent_app_type] => utility [patent_app_number] => 13/943893 [patent_app_country] => US [patent_app_date] => 2013-07-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 20 [patent_no_of_words] => 5737 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13943893 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/943893
Thin film transistor array substrate and method for manufacturing the same Jul 16, 2013 Issued
Array ( [id] => 10035349 [patent_doc_number] => 09076670 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-07-07 [patent_title] => 'Integrated circuit and method of forming the integrated circuit with improved logic transistor performance and SRAM transistor yield' [patent_app_type] => utility [patent_app_number] => 13/943786 [patent_app_country] => US [patent_app_date] => 2013-07-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 2691 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13943786 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/943786
Integrated circuit and method of forming the integrated circuit with improved logic transistor performance and SRAM transistor yield Jul 15, 2013 Issued
Array ( [id] => 9809748 [patent_doc_number] => 20150021693 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-01-22 [patent_title] => 'ENHANCING TRANSISTOR PERFORMANCE AND RELIABILITY BY INCORPORATING DEUTERIUM INTO A STRAINED CAPPING LAYER' [patent_app_type] => utility [patent_app_number] => 13/943521 [patent_app_country] => US [patent_app_date] => 2013-07-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 8463 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13943521 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/943521
Enhancing transistor performance and reliability by incorporating deuterium into a strained capping layer Jul 15, 2013 Issued
Array ( [id] => 9809827 [patent_doc_number] => 20150021772 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-01-22 [patent_title] => 'Mixed-metal barrier films optimized by high-productivity combinatorial PVD' [patent_app_type] => utility [patent_app_number] => 13/943418 [patent_app_country] => US [patent_app_date] => 2013-07-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 9213 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13943418 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/943418
Mixed-metal barrier films optimized by high-productivity combinatorial PVD Jul 15, 2013 Abandoned
Array ( [id] => 9394018 [patent_doc_number] => 20140091424 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-04-03 [patent_title] => 'COMPOUND SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF' [patent_app_type] => utility [patent_app_number] => 13/943427 [patent_app_country] => US [patent_app_date] => 2013-07-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 8797 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13943427 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/943427
COMPOUND SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF Jul 15, 2013 Abandoned
Array ( [id] => 9809736 [patent_doc_number] => 20150021681 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-01-22 [patent_title] => 'SEMICONDUCTOR DEVICE HAVING METAL GATE AND MANUFACTURING METHOD THEREOF' [patent_app_type] => utility [patent_app_number] => 13/943721 [patent_app_country] => US [patent_app_date] => 2013-07-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4536 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13943721 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/943721
SEMICONDUCTOR DEVICE HAVING METAL GATE AND MANUFACTURING METHOD THEREOF Jul 15, 2013 Abandoned
Array ( [id] => 11411622 [patent_doc_number] => 09558931 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-01-31 [patent_title] => 'System and method for gas-phase sulfur passivation of a semiconductor surface' [patent_app_type] => utility [patent_app_number] => 13/941216 [patent_app_country] => US [patent_app_date] => 2013-07-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 15 [patent_no_of_words] => 4546 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13941216 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/941216
System and method for gas-phase sulfur passivation of a semiconductor surface Jul 11, 2013 Issued
Array ( [id] => 10125951 [patent_doc_number] => 09160326 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-10-13 [patent_title] => 'Gate protected semiconductor devices' [patent_app_type] => utility [patent_app_number] => 13/936386 [patent_app_country] => US [patent_app_date] => 2013-07-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 22 [patent_no_of_words] => 9041 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13936386 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/936386
Gate protected semiconductor devices Jul 7, 2013 Issued
Array ( [id] => 10710146 [patent_doc_number] => 20160056293 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-02-25 [patent_title] => 'NON-PLANAR SEMICONDUCTOR DEVICE HAVING SELF-ALIGNED FIN WITH TOP BLOCKING LAYER' [patent_app_type] => utility [patent_app_number] => 14/780218 [patent_app_country] => US [patent_app_date] => 2013-06-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 7566 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14780218 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/780218
Non-planar semiconductor device having self-aligned fin with top blocking layer Jun 25, 2013 Issued
Array ( [id] => 9957893 [patent_doc_number] => 09006097 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-04-14 [patent_title] => 'Cu pillar bump with electrolytic metal sidewall protection' [patent_app_type] => utility [patent_app_number] => 13/927753 [patent_app_country] => US [patent_app_date] => 2013-06-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 3927 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13927753 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/927753
Cu pillar bump with electrolytic metal sidewall protection Jun 25, 2013 Issued
Array ( [id] => 11932663 [patent_doc_number] => 09799668 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-10-24 [patent_title] => 'Memory cell having isolated charge sites and method of fabricating same' [patent_app_type] => utility [patent_app_number] => 14/779938 [patent_app_country] => US [patent_app_date] => 2013-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 14 [patent_no_of_words] => 6405 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 158 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14779938 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/779938
Memory cell having isolated charge sites and method of fabricating same Jun 24, 2013 Issued
Array ( [id] => 9108633 [patent_doc_number] => 20130281765 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-10-24 [patent_title] => 'OBSERVER-BASED CANCELLATION SYSTEM FOR IMPLANTABLE HEARING INSTRUMENTS' [patent_app_type] => utility [patent_app_number] => 13/925444 [patent_app_country] => US [patent_app_date] => 2013-06-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 11606 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13925444 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/925444
Observer-based cancellation system for implantable hearing instruments Jun 23, 2013 Issued
Array ( [id] => 10710009 [patent_doc_number] => 20160056156 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-02-25 [patent_title] => 'NON-PLANAR SEMICONDUCTOR DEVICE HAVING DOPED SUB-FIN REGION AND METHOD TO FABRICATE SAME' [patent_app_type] => utility [patent_app_number] => 14/779936 [patent_app_country] => US [patent_app_date] => 2013-06-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 11641 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14779936 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/779936
Non-planar semiconductor device having doped sub-fin region and method to fabricate same Jun 19, 2013 Issued
Array ( [id] => 9203527 [patent_doc_number] => 20140002704 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-01-02 [patent_title] => 'SOLID-STATE IMAGING DEVICE AND ELECTRONIC DEVICE' [patent_app_type] => utility [patent_app_number] => 13/919450 [patent_app_country] => US [patent_app_date] => 2013-06-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 9962 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13919450 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/919450
Solid-state imaging device and electronic device Jun 16, 2013 Issued
Array ( [id] => 9418769 [patent_doc_number] => 20140103419 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-04-17 [patent_title] => 'NON-VOLATILE MEMORY DEVICE AND METHOD FOR FORMING THE SAME' [patent_app_type] => utility [patent_app_number] => 13/919365 [patent_app_country] => US [patent_app_date] => 2013-06-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 3366 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13919365 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/919365
NON-VOLATILE MEMORY DEVICE AND METHOD FOR FORMING THE SAME Jun 16, 2013 Abandoned
Array ( [id] => 11781983 [patent_doc_number] => 09391188 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-07-12 [patent_title] => 'Semiconductor device and method for fabricating semiconductor device' [patent_app_type] => utility [patent_app_number] => 13/916890 [patent_app_country] => US [patent_app_date] => 2013-06-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 22 [patent_no_of_words] => 9928 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 210 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13916890 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/916890
Semiconductor device and method for fabricating semiconductor device Jun 12, 2013 Issued
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