
Don P. Le
Examiner (ID: 5300, Phone: (571)272-1806 , Office: P/2844 )
| Most Active Art Unit | 2819 |
| Art Unit(s) | 2844, 2819 |
| Total Applications | 2669 |
| Issued Applications | 2528 |
| Pending Applications | 46 |
| Abandoned Applications | 99 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 4572545
[patent_doc_number] => 07847589
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2010-12-07
[patent_title] => 'Configuration data feeding device'
[patent_app_type] => utility
[patent_app_number] => 12/625730
[patent_app_country] => US
[patent_app_date] => 2009-11-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 10
[patent_no_of_words] => 4365
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 106
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/847/07847589.pdf
[firstpage_image] =>[orig_patent_app_number] => 12625730
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/625730 | Configuration data feeding device | Nov 24, 2009 | Issued |
Array
(
[id] => 6231925
[patent_doc_number] => 20100264956
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2010-10-21
[patent_title] => 'Inverter, method of manufacturing the same, and logic circuit including the inverter'
[patent_app_type] => utility
[patent_app_number] => 12/591654
[patent_app_country] => US
[patent_app_date] => 2009-11-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 20
[patent_figures_cnt] => 20
[patent_no_of_words] => 11712
[patent_no_of_claims] => 32
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0264/20100264956.pdf
[firstpage_image] =>[orig_patent_app_number] => 12591654
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/591654 | Inverter, method of manufacturing the same, and logic circuit including the inverter | Nov 24, 2009 | Issued |
Array
(
[id] => 6146218
[patent_doc_number] => 20110018583
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2011-01-27
[patent_title] => 'HIGH VOLTAGE LOGIC CIRCUITS'
[patent_app_type] => utility
[patent_app_number] => 12/619562
[patent_app_country] => US
[patent_app_date] => 2009-11-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 6924
[patent_no_of_claims] => 25
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0018/20110018583.pdf
[firstpage_image] =>[orig_patent_app_number] => 12619562
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/619562 | High voltage logic circuits | Nov 15, 2009 | Issued |
Array
(
[id] => 4588015
[patent_doc_number] => 07852115
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2010-12-14
[patent_title] => 'Method and apparatus for safe power up of programmable interconnect'
[patent_app_type] => utility
[patent_app_number] => 12/608499
[patent_app_country] => US
[patent_app_date] => 2009-10-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 8
[patent_no_of_words] => 3542
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 15
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/852/07852115.pdf
[firstpage_image] =>[orig_patent_app_number] => 12608499
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/608499 | Method and apparatus for safe power up of programmable interconnect | Oct 28, 2009 | Issued |
Array
(
[id] => 7530994
[patent_doc_number] => 07843218
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2010-11-30
[patent_title] => 'Data latch with structural hold'
[patent_app_type] => utility
[patent_app_number] => 12/607657
[patent_app_country] => US
[patent_app_date] => 2009-10-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 12
[patent_no_of_words] => 10754
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 140
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/843/07843218.pdf
[firstpage_image] =>[orig_patent_app_number] => 12607657
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/607657 | Data latch with structural hold | Oct 27, 2009 | Issued |
Array
(
[id] => 6605740
[patent_doc_number] => 20100033211
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2010-02-11
[patent_title] => 'Link transmitter with reduced power consumption'
[patent_app_type] => utility
[patent_app_number] => 12/587775
[patent_app_country] => US
[patent_app_date] => 2009-10-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 2592
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0033/20100033211.pdf
[firstpage_image] =>[orig_patent_app_number] => 12587775
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/587775 | Link transmitter with reduced power consumption | Oct 12, 2009 | Abandoned |
Array
(
[id] => 4566242
[patent_doc_number] => 07839165
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2010-11-23
[patent_title] => 'User-accessible freeze-logic for dynamic power reduction and associated methods'
[patent_app_type] => utility
[patent_app_number] => 12/577061
[patent_app_country] => US
[patent_app_date] => 2009-10-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 12
[patent_no_of_words] => 6299
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 42
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/839/07839165.pdf
[firstpage_image] =>[orig_patent_app_number] => 12577061
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/577061 | User-accessible freeze-logic for dynamic power reduction and associated methods | Oct 8, 2009 | Issued |
Array
(
[id] => 4614732
[patent_doc_number] => 07990176
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2011-08-02
[patent_title] => 'Low power line driver and method thereof'
[patent_app_type] => utility
[patent_app_number] => 12/565339
[patent_app_country] => US
[patent_app_date] => 2009-09-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 8
[patent_no_of_words] => 3236
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 94
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/990/07990176.pdf
[firstpage_image] =>[orig_patent_app_number] => 12565339
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/565339 | Low power line driver and method thereof | Sep 22, 2009 | Issued |
Array
(
[id] => 6403830
[patent_doc_number] => 20100148817
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2010-06-17
[patent_title] => 'Reduced power output buffer'
[patent_app_type] => utility
[patent_app_number] => 12/586288
[patent_app_country] => US
[patent_app_date] => 2009-09-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 3564
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0148/20100148817.pdf
[firstpage_image] =>[orig_patent_app_number] => 12586288
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/586288 | Reduced power output buffer | Sep 17, 2009 | Issued |
Array
(
[id] => 4601139
[patent_doc_number] => 07977975
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2011-07-12
[patent_title] => 'Apparatus for using metastability-hardened storage circuits in logic devices and associated methods'
[patent_app_type] => utility
[patent_app_number] => 12/563088
[patent_app_country] => US
[patent_app_date] => 2009-09-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 16
[patent_figures_cnt] => 19
[patent_no_of_words] => 6737
[patent_no_of_claims] => 28
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 35
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/977/07977975.pdf
[firstpage_image] =>[orig_patent_app_number] => 12563088
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/563088 | Apparatus for using metastability-hardened storage circuits in logic devices and associated methods | Sep 17, 2009 | Issued |
Array
(
[id] => 7968485
[patent_doc_number] => 07940085
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2011-05-10
[patent_title] => 'Inverter, method of operating the same and logic circuit comprising inverter'
[patent_app_type] => utility
[patent_app_number] => 12/585557
[patent_app_country] => US
[patent_app_date] => 2009-09-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 16
[patent_figures_cnt] => 16
[patent_no_of_words] => 8872
[patent_no_of_claims] => 26
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 46
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/940/07940085.pdf
[firstpage_image] =>[orig_patent_app_number] => 12585557
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/585557 | Inverter, method of operating the same and logic circuit comprising inverter | Sep 16, 2009 | Issued |
Array
(
[id] => 6568220
[patent_doc_number] => 20100060313
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2010-03-11
[patent_title] => 'Semiconductor integrated circuit device and test terminal arrangement method'
[patent_app_type] => utility
[patent_app_number] => 12/585206
[patent_app_country] => US
[patent_app_date] => 2009-09-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 3511
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0060/20100060313.pdf
[firstpage_image] =>[orig_patent_app_number] => 12585206
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/585206 | Semiconductor integrated circuit device and test terminal arrangement method | Sep 7, 2009 | Issued |
Array
(
[id] => 4566191
[patent_doc_number] => 07839161
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2010-11-23
[patent_title] => 'Low-jitter high-frequency clock channel'
[patent_app_type] => utility
[patent_app_number] => 12/555564
[patent_app_country] => US
[patent_app_date] => 2009-09-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 4952
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 9
[patent_words_short_claim] => 19
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/839/07839161.pdf
[firstpage_image] =>[orig_patent_app_number] => 12555564
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/555564 | Low-jitter high-frequency clock channel | Sep 7, 2009 | Issued |
Array
(
[id] => 6355300
[patent_doc_number] => 20100073027
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2010-03-25
[patent_title] => 'LATCH STRUCTURE, FREQUENCY DIVIDER, AND METHODS FOR OPERATING SAME'
[patent_app_type] => utility
[patent_app_number] => 12/552810
[patent_app_country] => US
[patent_app_date] => 2009-09-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 4229
[patent_no_of_claims] => 26
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0073/20100073027.pdf
[firstpage_image] =>[orig_patent_app_number] => 12552810
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/552810 | Latch structure, frequency divider, and methods for operating same | Sep 1, 2009 | Issued |
Array
(
[id] => 4580385
[patent_doc_number] => 07825694
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2010-11-02
[patent_title] => 'Differential output circuit'
[patent_app_type] => utility
[patent_app_number] => 12/551978
[patent_app_country] => US
[patent_app_date] => 2009-09-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 16
[patent_figures_cnt] => 17
[patent_no_of_words] => 7907
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 155
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/825/07825694.pdf
[firstpage_image] =>[orig_patent_app_number] => 12551978
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/551978 | Differential output circuit | Aug 31, 2009 | Issued |
Array
(
[id] => 4580376
[patent_doc_number] => 07825693
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2010-11-02
[patent_title] => 'Reduced duty cycle distortion using controlled body device'
[patent_app_type] => utility
[patent_app_number] => 12/550877
[patent_app_country] => US
[patent_app_date] => 2009-08-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 14
[patent_no_of_words] => 4303
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 139
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/825/07825693.pdf
[firstpage_image] =>[orig_patent_app_number] => 12550877
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/550877 | Reduced duty cycle distortion using controlled body device | Aug 30, 2009 | Issued |
Array
(
[id] => 6537666
[patent_doc_number] => 20100270941
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2010-10-28
[patent_title] => 'APPARATUS AND METHODS OF OPERATION OF PASSIVE LED LIGHTING EQUIPMENT'
[patent_app_type] => utility
[patent_app_number] => 12/544545
[patent_app_country] => US
[patent_app_date] => 2009-08-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 29
[patent_figures_cnt] => 29
[patent_no_of_words] => 8423
[patent_no_of_claims] => 51
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0270/20100270941.pdf
[firstpage_image] =>[orig_patent_app_number] => 12544545
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/544545 | Apparatus and methods of operation of passive LED lighting equipment | Aug 19, 2009 | Issued |
Array
(
[id] => 6068269
[patent_doc_number] => 20110043118
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2011-02-24
[patent_title] => 'LIGHT-EMITTING DIODE BACKLIGHTING SYSTEMS'
[patent_app_type] => utility
[patent_app_number] => 12/543722
[patent_app_country] => US
[patent_app_date] => 2009-08-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 3155
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0043/20110043118.pdf
[firstpage_image] =>[orig_patent_app_number] => 12543722
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/543722 | Light-emitting diode backlighting systems | Aug 18, 2009 | Issued |
Array
(
[id] => 8258183
[patent_doc_number] => 08207682
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2012-06-26
[patent_title] => 'Light source control device and method'
[patent_app_type] => utility
[patent_app_number] => 12/544030
[patent_app_country] => US
[patent_app_date] => 2009-08-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 10
[patent_no_of_words] => 5198
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 95
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12544030
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/544030 | Light source control device and method | Aug 18, 2009 | Issued |
Array
(
[id] => 9233501
[patent_doc_number] => 08598809
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2013-12-03
[patent_title] => 'White light color changing solid state lighting and methods'
[patent_app_type] => utility
[patent_app_number] => 12/544131
[patent_app_country] => US
[patent_app_date] => 2009-08-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 7
[patent_no_of_words] => 6107
[patent_no_of_claims] => 38
[patent_no_of_ind_claims] => 16
[patent_words_short_claim] => 86
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12544131
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/544131 | White light color changing solid state lighting and methods | Aug 18, 2009 | Issued |