
Don P. Le
Examiner (ID: 5300, Phone: (571)272-1806 , Office: P/2844 )
| Most Active Art Unit | 2819 |
| Art Unit(s) | 2844, 2819 |
| Total Applications | 2669 |
| Issued Applications | 2528 |
| Pending Applications | 46 |
| Abandoned Applications | 99 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 5328398
[patent_doc_number] => 20090108875
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2009-04-30
[patent_title] => 'Structure for a Limited Switch Dynamic Logic Cell Based Register'
[patent_app_type] => utility
[patent_app_number] => 12/174543
[patent_app_country] => US
[patent_app_date] => 2008-07-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 5403
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0108/20090108875.pdf
[firstpage_image] =>[orig_patent_app_number] => 12174543
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/174543 | Structure for a Limited Switch Dynamic Logic Cell Based Register | Jul 15, 2008 | Abandoned |
Array
(
[id] => 65471
[patent_doc_number] => 07759973
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2010-07-20
[patent_title] => 'Integrated circuit having embedded differential clock tree'
[patent_app_type] => utility
[patent_app_number] => 12/174502
[patent_app_country] => US
[patent_app_date] => 2008-07-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 32
[patent_figures_cnt] => 32
[patent_no_of_words] => 17337
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 69
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/759/07759973.pdf
[firstpage_image] =>[orig_patent_app_number] => 12174502
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/174502 | Integrated circuit having embedded differential clock tree | Jul 15, 2008 | Issued |
Array
(
[id] => 278538
[patent_doc_number] => 07557616
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2009-07-07
[patent_title] => 'Limited switch dynamic logic cell based register'
[patent_app_type] => utility
[patent_app_number] => 12/172656
[patent_app_country] => US
[patent_app_date] => 2008-07-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 12
[patent_no_of_words] => 4385
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 140
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/557/07557616.pdf
[firstpage_image] =>[orig_patent_app_number] => 12172656
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/172656 | Limited switch dynamic logic cell based register | Jul 13, 2008 | Issued |
Array
(
[id] => 4857092
[patent_doc_number] => 20080265942
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-10-30
[patent_title] => 'DIFFERENTIAL AMPLIFIER, DIGITAL-TO-ANALOG CONVERTER AND DISPLAY APPARATUS'
[patent_app_type] => utility
[patent_app_number] => 12/166098
[patent_app_country] => US
[patent_app_date] => 2008-07-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 20
[patent_figures_cnt] => 20
[patent_no_of_words] => 13667
[patent_no_of_claims] => 28
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0265/20080265942.pdf
[firstpage_image] =>[orig_patent_app_number] => 12166098
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/166098 | Differential amplifier, digital-to-analog converter and display apparatus | Jun 30, 2008 | Issued |
Array
(
[id] => 178476
[patent_doc_number] => 07656186
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2010-02-02
[patent_title] => 'Calibration circuit, semiconductor device including the same, and data processing system'
[patent_app_type] => utility
[patent_app_number] => 12/213962
[patent_app_country] => US
[patent_app_date] => 2008-06-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 12
[patent_no_of_words] => 8019
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 199
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/656/07656186.pdf
[firstpage_image] =>[orig_patent_app_number] => 12213962
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/213962 | Calibration circuit, semiconductor device including the same, and data processing system | Jun 25, 2008 | Issued |
Array
(
[id] => 186290
[patent_doc_number] => 07646218
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2010-01-12
[patent_title] => 'Architecture and interconnect scheme for programmable logic circuits'
[patent_app_type] => utility
[patent_app_number] => 12/215118
[patent_app_country] => US
[patent_app_date] => 2008-06-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 15
[patent_no_of_words] => 7836
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 308
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/646/07646218.pdf
[firstpage_image] =>[orig_patent_app_number] => 12215118
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/215118 | Architecture and interconnect scheme for programmable logic circuits | Jun 23, 2008 | Issued |
Array
(
[id] => 7590806
[patent_doc_number] => 07663407
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2010-02-16
[patent_title] => 'Semiconductor device having transfer gate between pre-buffer and main buffer'
[patent_app_type] => utility
[patent_app_number] => 12/213780
[patent_app_country] => US
[patent_app_date] => 2008-06-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 12
[patent_no_of_words] => 8904
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 74
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/663/07663407.pdf
[firstpage_image] =>[orig_patent_app_number] => 12213780
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/213780 | Semiconductor device having transfer gate between pre-buffer and main buffer | Jun 23, 2008 | Issued |
Array
(
[id] => 6323457
[patent_doc_number] => 20100244697
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2010-09-30
[patent_title] => 'MOTOR VEHICLE HAVING A HATCHBACK'
[patent_app_type] => utility
[patent_app_number] => 12/666554
[patent_app_country] => US
[patent_app_date] => 2008-06-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 3255
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0244/20100244697.pdf
[firstpage_image] =>[orig_patent_app_number] => 12666554
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/666554 | Motor vehicle having a hatchback | Jun 22, 2008 | Issued |
Array
(
[id] => 4518826
[patent_doc_number] => 07932744
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2011-04-26
[patent_title] => 'Staggered I/O groups for integrated circuits'
[patent_app_type] => utility
[patent_app_number] => 12/142118
[patent_app_country] => US
[patent_app_date] => 2008-06-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 15
[patent_no_of_words] => 6142
[patent_no_of_claims] => 28
[patent_no_of_ind_claims] => 9
[patent_words_short_claim] => 87
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/932/07932744.pdf
[firstpage_image] =>[orig_patent_app_number] => 12142118
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/142118 | Staggered I/O groups for integrated circuits | Jun 18, 2008 | Issued |
Array
(
[id] => 17059
[patent_doc_number] => 07809347
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2010-10-05
[patent_title] => 'Modular ASIC with crosspoint switch'
[patent_app_type] => utility
[patent_app_number] => 12/142551
[patent_app_country] => US
[patent_app_date] => 2008-06-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 4
[patent_no_of_words] => 3607
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 161
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/809/07809347.pdf
[firstpage_image] =>[orig_patent_app_number] => 12142551
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/142551 | Modular ASIC with crosspoint switch | Jun 18, 2008 | Issued |
Array
(
[id] => 278534
[patent_doc_number] => 07557612
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2009-07-07
[patent_title] => 'Block symmetrization in a field programmable gate array'
[patent_app_type] => utility
[patent_app_number] => 12/130876
[patent_app_country] => US
[patent_app_date] => 2008-05-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 7898
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 408
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/557/07557612.pdf
[firstpage_image] =>[orig_patent_app_number] => 12130876
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/130876 | Block symmetrization in a field programmable gate array | May 29, 2008 | Issued |
Array
(
[id] => 373812
[patent_doc_number] => 07474117
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2009-01-06
[patent_title] => 'Bi-directional universal serial bus booster circuit'
[patent_app_type] => utility
[patent_app_number] => 12/127165
[patent_app_country] => US
[patent_app_date] => 2008-05-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 2090
[patent_no_of_claims] => 1
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 195
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/474/07474117.pdf
[firstpage_image] =>[orig_patent_app_number] => 12127165
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/127165 | Bi-directional universal serial bus booster circuit | May 26, 2008 | Issued |
Array
(
[id] => 4696022
[patent_doc_number] => 20080218206
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-09-11
[patent_title] => 'FIELD PROGRAMMABLE GATE ARRAY LONG LINE ROUTING NETWORK'
[patent_app_type] => utility
[patent_app_number] => 12/127516
[patent_app_country] => US
[patent_app_date] => 2008-05-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 4404
[patent_no_of_claims] => 1
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0218/20080218206.pdf
[firstpage_image] =>[orig_patent_app_number] => 12127516
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/127516 | FIELD PROGRAMMABLE GATE ARRAY LONG LINE ROUTING NETWORK | May 26, 2008 | Abandoned |
Array
(
[id] => 4789925
[patent_doc_number] => 20080290898
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-11-27
[patent_title] => 'PROGRAMMABLE LOGIC DEVICE HAVING COMPLEX LOGIC BLOCKS WITH IMPROVED LOGIC CELL FUNCTIONALITY'
[patent_app_type] => utility
[patent_app_number] => 12/125824
[patent_app_country] => US
[patent_app_date] => 2008-05-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 14
[patent_figures_cnt] => 14
[patent_no_of_words] => 3951
[patent_no_of_claims] => 1
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0290/20080290898.pdf
[firstpage_image] =>[orig_patent_app_number] => 12125824
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/125824 | Programmable logic device having complex logic blocks with improved logic cell functionality | May 21, 2008 | Issued |
Array
(
[id] => 4885373
[patent_doc_number] => 20080259705
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-10-23
[patent_title] => 'HARDWARE AND SOFTWARE PROGRAMMABLE FUSES FOR MEMORY REPAIR'
[patent_app_type] => utility
[patent_app_number] => 12/122932
[patent_app_country] => US
[patent_app_date] => 2008-05-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 30
[patent_figures_cnt] => 30
[patent_no_of_words] => 15334
[patent_no_of_claims] => 43
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0259/20080259705.pdf
[firstpage_image] =>[orig_patent_app_number] => 12122932
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/122932 | Hardware and software programmable fuses for memory repair | May 18, 2008 | Issued |
Array
(
[id] => 260563
[patent_doc_number] => 07573293
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2009-08-11
[patent_title] => 'Programmable logic based latches and shift registers'
[patent_app_type] => utility
[patent_app_number] => 12/119490
[patent_app_country] => US
[patent_app_date] => 2008-05-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 13
[patent_no_of_words] => 6346
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 79
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/573/07573293.pdf
[firstpage_image] =>[orig_patent_app_number] => 12119490
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/119490 | Programmable logic based latches and shift registers | May 11, 2008 | Issued |
Array
(
[id] => 260564
[patent_doc_number] => 07573294
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2009-08-11
[patent_title] => 'Programmable logic based latches and shift registers'
[patent_app_type] => utility
[patent_app_number] => 12/119492
[patent_app_country] => US
[patent_app_date] => 2008-05-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 13
[patent_no_of_words] => 6351
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 77
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/573/07573294.pdf
[firstpage_image] =>[orig_patent_app_number] => 12119492
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/119492 | Programmable logic based latches and shift registers | May 11, 2008 | Issued |
Array
(
[id] => 282355
[patent_doc_number] => 07554356
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2009-06-30
[patent_title] => 'Adding or subtracting inputs using a carry signal with a fixed value of logic 0'
[patent_app_type] => utility
[patent_app_number] => 12/119323
[patent_app_country] => US
[patent_app_date] => 2008-05-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 18
[patent_figures_cnt] => 18
[patent_no_of_words] => 6250
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 25
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/554/07554356.pdf
[firstpage_image] =>[orig_patent_app_number] => 12119323
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/119323 | Adding or subtracting inputs using a carry signal with a fixed value of logic 0 | May 11, 2008 | Issued |
Array
(
[id] => 113149
[patent_doc_number] => 07719304
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2010-05-18
[patent_title] => 'Radiation hardened master-slave flip-flop'
[patent_app_type] => utility
[patent_app_number] => 12/117320
[patent_app_country] => US
[patent_app_date] => 2008-05-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 15
[patent_no_of_words] => 9511
[patent_no_of_claims] => 24
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 157
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/719/07719304.pdf
[firstpage_image] =>[orig_patent_app_number] => 12117320
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/117320 | Radiation hardened master-slave flip-flop | May 7, 2008 | Issued |
Array
(
[id] => 4789927
[patent_doc_number] => 20080290900
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-11-27
[patent_title] => 'Two-Stage Level Shifting Module'
[patent_app_type] => utility
[patent_app_number] => 12/114814
[patent_app_country] => US
[patent_app_date] => 2008-05-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 5520
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0290/20080290900.pdf
[firstpage_image] =>[orig_patent_app_number] => 12114814
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/114814 | Two-stage level shifting module | May 3, 2008 | Issued |