Search

Don P. Le

Examiner (ID: 5300, Phone: (571)272-1806 , Office: P/2844 )

Most Active Art Unit
2819
Art Unit(s)
2844, 2819
Total Applications
2669
Issued Applications
2528
Pending Applications
46
Abandoned Applications
99

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4576996 [patent_doc_number] => 07859312 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-12-28 [patent_title] => 'Multivalued logic circuit' [patent_app_type] => utility [patent_app_number] => 12/598669 [patent_app_country] => US [patent_app_date] => 2008-04-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 5 [patent_no_of_words] => 4200 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 191 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/859/07859312.pdf [firstpage_image] =>[orig_patent_app_number] => 12598669 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/598669
Multivalued logic circuit Apr 29, 2008 Issued
Array ( [id] => 5399694 [patent_doc_number] => 20090319757 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-12-24 [patent_title] => 'ARCHITECTURE FOR LOCAL PROGRAMMING OF QUANTUM PROCESSOR ELEMENTS USING LATCHING QUBITS' [patent_app_type] => utility [patent_app_number] => 12/109847 [patent_app_country] => US [patent_app_date] => 2008-04-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 10880 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0319/20090319757.pdf [firstpage_image] =>[orig_patent_app_number] => 12109847 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/109847
Architecture for local programming of quantum processor elements using latching qubits Apr 24, 2008 Issued
Array ( [id] => 5556062 [patent_doc_number] => 20090267639 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-10-29 [patent_title] => 'INPUT CANCELLATION CIRCUIT' [patent_app_type] => utility [patent_app_number] => 12/108873 [patent_app_country] => US [patent_app_date] => 2008-04-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2830 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0267/20090267639.pdf [firstpage_image] =>[orig_patent_app_number] => 12108873 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/108873
Input cancellation circuit Apr 23, 2008 Issued
Array ( [id] => 274786 [patent_doc_number] => 07560953 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2009-07-14 [patent_title] => 'Power management systems and methods for programmable logic devices' [patent_app_type] => utility [patent_app_number] => 12/107883 [patent_app_country] => US [patent_app_date] => 2008-04-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 3552 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/560/07560953.pdf [firstpage_image] =>[orig_patent_app_number] => 12107883 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/107883
Power management systems and methods for programmable logic devices Apr 22, 2008 Issued
Array ( [id] => 163587 [patent_doc_number] => 07671627 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2010-03-02 [patent_title] => 'Superscale processor performance enhancement through reliable dynamic clock frequency tuning' [patent_app_type] => utility [patent_app_number] => 12/107415 [patent_app_country] => US [patent_app_date] => 2008-04-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 10155 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/671/07671627.pdf [firstpage_image] =>[orig_patent_app_number] => 12107415 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/107415
Superscale processor performance enhancement through reliable dynamic clock frequency tuning Apr 21, 2008 Issued
Array ( [id] => 5493831 [patent_doc_number] => 20090261859 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-10-22 [patent_title] => 'RECEIVER CIRCUITRY FOR RECEIVING REDUCED SWING SIGNALS FROM A CHANNEL' [patent_app_type] => utility [patent_app_number] => 12/106522 [patent_app_country] => US [patent_app_date] => 2008-04-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 5495 [patent_no_of_claims] => 42 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0261/20090261859.pdf [firstpage_image] =>[orig_patent_app_number] => 12106522 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/106522
Receiver circuitry for receiving reduced swing signals from a channel Apr 20, 2008 Issued
Array ( [id] => 225415 [patent_doc_number] => 07605601 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-10-20 [patent_title] => 'Semiconductor integrated circuit device' [patent_app_type] => utility [patent_app_number] => 12/105638 [patent_app_country] => US [patent_app_date] => 2008-04-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 53 [patent_no_of_words] => 16010 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/605/07605601.pdf [firstpage_image] =>[orig_patent_app_number] => 12105638 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/105638
Semiconductor integrated circuit device Apr 17, 2008 Issued
Array ( [id] => 212048 [patent_doc_number] => 07622955 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-11-24 [patent_title] => 'Power savings with a level-shifting boundary isolation flip-flop (LSIFF) and a clock controlled data retention scheme' [patent_app_type] => utility [patent_app_number] => 12/104580 [patent_app_country] => US [patent_app_date] => 2008-04-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 10096 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/622/07622955.pdf [firstpage_image] =>[orig_patent_app_number] => 12104580 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/104580
Power savings with a level-shifting boundary isolation flip-flop (LSIFF) and a clock controlled data retention scheme Apr 16, 2008 Issued
Array ( [id] => 278528 [patent_doc_number] => 07557606 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2009-07-07 [patent_title] => 'Synchronization of data signals and clock signals for programmable logic devices' [patent_app_type] => utility [patent_app_number] => 12/105146 [patent_app_country] => US [patent_app_date] => 2008-04-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 6275 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/557/07557606.pdf [firstpage_image] =>[orig_patent_app_number] => 12105146 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/105146
Synchronization of data signals and clock signals for programmable logic devices Apr 16, 2008 Issued
Array ( [id] => 300371 [patent_doc_number] => 07538575 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-05-26 [patent_title] => 'Three dimensional integrated circuits' [patent_app_type] => utility [patent_app_number] => 12/105259 [patent_app_country] => US [patent_app_date] => 2008-04-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 17 [patent_no_of_words] => 7155 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 46 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/538/07538575.pdf [firstpage_image] =>[orig_patent_app_number] => 12105259 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/105259
Three dimensional integrated circuits Apr 16, 2008 Issued
12/104331 HIGH PERFORMANCE INTERCONNECT ARCHITECTURE FOR FIELD PROGRAMMABLE GATE ARRAYS Apr 15, 2008 Abandoned
Array ( [id] => 4811106 [patent_doc_number] => 20080191737 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-08-14 [patent_title] => 'Reconfigurable sequencer structure' [patent_app_type] => utility [patent_app_number] => 12/082073 [patent_app_country] => US [patent_app_date] => 2008-04-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 7495 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 17 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0191/20080191737.pdf [firstpage_image] =>[orig_patent_app_number] => 12082073 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/082073
Reconfigurable sequencer structure Apr 6, 2008 Issued
Array ( [id] => 55394 [patent_doc_number] => 07768310 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-08-03 [patent_title] => 'Semiconductor device, method of switching drive capability of the semiconductor device, and system including semiconductor devices' [patent_app_type] => utility [patent_app_number] => 12/061458 [patent_app_country] => US [patent_app_date] => 2008-04-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3209 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/768/07768310.pdf [firstpage_image] =>[orig_patent_app_number] => 12061458 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/061458
Semiconductor device, method of switching drive capability of the semiconductor device, and system including semiconductor devices Apr 1, 2008 Issued
Array ( [id] => 4844579 [patent_doc_number] => 20080180987 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-07-31 [patent_title] => 'Multi-State Latches From n-State Reversible Inverters' [patent_app_type] => utility [patent_app_number] => 12/061286 [patent_app_country] => US [patent_app_date] => 2008-04-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 11408 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0180/20080180987.pdf [firstpage_image] =>[orig_patent_app_number] => 12061286 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/061286
Multi-state latches from n-state reversible inverters Apr 1, 2008 Issued
Array ( [id] => 580904 [patent_doc_number] => 07459935 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2008-12-02 [patent_title] => 'Programmable logic devices with distributed memory' [patent_app_type] => utility [patent_app_number] => 12/060776 [patent_app_country] => US [patent_app_date] => 2008-04-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 11 [patent_no_of_words] => 2953 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/459/07459935.pdf [firstpage_image] =>[orig_patent_app_number] => 12060776 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/060776
Programmable logic devices with distributed memory Mar 31, 2008 Issued
Array ( [id] => 565566 [patent_doc_number] => 07471104 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2008-12-30 [patent_title] => 'Lookup table with relatively balanced delays' [patent_app_type] => utility [patent_app_number] => 12/059021 [patent_app_country] => US [patent_app_date] => 2008-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 10 [patent_no_of_words] => 5085 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/471/07471104.pdf [firstpage_image] =>[orig_patent_app_number] => 12059021 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/059021
Lookup table with relatively balanced delays Mar 30, 2008 Issued
Array ( [id] => 5470518 [patent_doc_number] => 20090243684 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-10-01 [patent_title] => 'METHOD AND DEVICE FOR GENERATING A DIGITAL DATA SIGNAL AND USE THEREOF' [patent_app_type] => utility [patent_app_number] => 12/058671 [patent_app_country] => US [patent_app_date] => 2008-03-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4947 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0243/20090243684.pdf [firstpage_image] =>[orig_patent_app_number] => 12058671 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/058671
Method and device for generating a digital data signal and use thereof Mar 28, 2008 Issued
Array ( [id] => 4764116 [patent_doc_number] => 20080175327 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-07-24 [patent_title] => 'SYSTEM FOR REDUCING CROSS-TALK INDUCED SOURCE SYNCHRONOUS BUS CLOCK JITTER' [patent_app_type] => utility [patent_app_number] => 12/058689 [patent_app_country] => US [patent_app_date] => 2008-03-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 4096 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0175/20080175327.pdf [firstpage_image] =>[orig_patent_app_number] => 12058689 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/058689
System for reducing cross-talk induced source synchronous bus clock jitter Mar 28, 2008 Issued
Array ( [id] => 197876 [patent_doc_number] => 07639047 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2009-12-29 [patent_title] => 'Techniques for reducing clock skew in clock routing networks' [patent_app_type] => utility [patent_app_number] => 12/053573 [patent_app_country] => US [patent_app_date] => 2008-03-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 6911 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/639/07639047.pdf [firstpage_image] =>[orig_patent_app_number] => 12053573 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/053573
Techniques for reducing clock skew in clock routing networks Mar 21, 2008 Issued
Array ( [id] => 575974 [patent_doc_number] => 07463059 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-12-09 [patent_title] => 'Alterable application specific integrated circuit (ASIC)' [patent_app_type] => utility [patent_app_number] => 12/045635 [patent_app_country] => US [patent_app_date] => 2008-03-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 23 [patent_no_of_words] => 10229 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/463/07463059.pdf [firstpage_image] =>[orig_patent_app_number] => 12045635 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/045635
Alterable application specific integrated circuit (ASIC) Mar 9, 2008 Issued
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