Search

Don P. Le

Examiner (ID: 5300, Phone: (571)272-1806 , Office: P/2844 )

Most Active Art Unit
2819
Art Unit(s)
2844, 2819
Total Applications
2669
Issued Applications
2528
Pending Applications
46
Abandoned Applications
99

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 289476 [patent_doc_number] => 07548093 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2009-06-16 [patent_title] => 'Scheme of level shifter cell' [patent_app_type] => utility [patent_app_number] => 12/042351 [patent_app_country] => US [patent_app_date] => 2008-03-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2987 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/548/07548093.pdf [firstpage_image] =>[orig_patent_app_number] => 12042351 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/042351
Scheme of level shifter cell Mar 4, 2008 Issued
Array ( [id] => 7597137 [patent_doc_number] => 07619441 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2009-11-17 [patent_title] => 'Apparatus for interconnecting stacked dice on a programmable integrated circuit' [patent_app_type] => utility [patent_app_number] => 12/041612 [patent_app_country] => US [patent_app_date] => 2008-03-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 4969 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 56 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/619/07619441.pdf [firstpage_image] =>[orig_patent_app_number] => 12041612 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/041612
Apparatus for interconnecting stacked dice on a programmable integrated circuit Mar 2, 2008 Issued
Array ( [id] => 225417 [patent_doc_number] => 07605603 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2009-10-20 [patent_title] => 'User-accessible freeze-logic for dynamic power reduction and associated methods' [patent_app_type] => utility [patent_app_number] => 12/040100 [patent_app_country] => US [patent_app_date] => 2008-02-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 12 [patent_no_of_words] => 6249 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 45 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/605/07605603.pdf [firstpage_image] =>[orig_patent_app_number] => 12040100 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/040100
User-accessible freeze-logic for dynamic power reduction and associated methods Feb 28, 2008 Issued
Array ( [id] => 243821 [patent_doc_number] => 07589558 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2009-09-15 [patent_title] => 'Method and apparatus for configuring an integrated circuit' [patent_app_type] => utility [patent_app_number] => 12/038763 [patent_app_country] => US [patent_app_date] => 2008-02-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 10 [patent_no_of_words] => 5623 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/589/07589558.pdf [firstpage_image] =>[orig_patent_app_number] => 12038763 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/038763
Method and apparatus for configuring an integrated circuit Feb 26, 2008 Issued
Array ( [id] => 7595046 [patent_doc_number] => 07626415 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2009-12-01 [patent_title] => 'Method and apparatus for configuring an integrated circuit' [patent_app_type] => utility [patent_app_number] => 12/038768 [patent_app_country] => US [patent_app_date] => 2008-02-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 3961 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 51 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/626/07626415.pdf [firstpage_image] =>[orig_patent_app_number] => 12038768 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/038768
Method and apparatus for configuring an integrated circuit Feb 26, 2008 Issued
Array ( [id] => 212047 [patent_doc_number] => 07622954 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-11-24 [patent_title] => 'Level shifter with memory interfacing two supply domains' [patent_app_type] => utility [patent_app_number] => 12/037639 [patent_app_country] => US [patent_app_date] => 2008-02-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 5879 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/622/07622954.pdf [firstpage_image] =>[orig_patent_app_number] => 12037639 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/037639
Level shifter with memory interfacing two supply domains Feb 25, 2008 Issued
Array ( [id] => 240118 [patent_doc_number] => 07592838 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-09-22 [patent_title] => 'Method for communicating data and clock signals and corresponding signal, transmitter and receiver' [patent_app_type] => utility [patent_app_number] => 12/036753 [patent_app_country] => US [patent_app_date] => 2008-02-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 7 [patent_no_of_words] => 2905 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/592/07592838.pdf [firstpage_image] =>[orig_patent_app_number] => 12036753 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/036753
Method for communicating data and clock signals and corresponding signal, transmitter and receiver Feb 24, 2008 Issued
Array ( [id] => 4673907 [patent_doc_number] => 20080211535 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-09-04 [patent_title] => 'Pseudo-differential output driver with high immunity to noise and jitter' [patent_app_type] => utility [patent_app_number] => 12/072110 [patent_app_country] => US [patent_app_date] => 2008-02-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2749 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0211/20080211535.pdf [firstpage_image] =>[orig_patent_app_number] => 12072110 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/072110
Pseudo-differential output driver with high immunity to noise and jitter Feb 20, 2008 Issued
Array ( [id] => 278533 [patent_doc_number] => 07557611 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-07-07 [patent_title] => 'Block level routing architecture in a field programmable gate array' [patent_app_type] => utility [patent_app_number] => 12/034555 [patent_app_country] => US [patent_app_date] => 2008-02-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 8231 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 295 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/557/07557611.pdf [firstpage_image] =>[orig_patent_app_number] => 12034555 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/034555
Block level routing architecture in a field programmable gate array Feb 19, 2008 Issued
Array ( [id] => 5263879 [patent_doc_number] => 20090116564 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-05-07 [patent_title] => 'LOW VOLTAGE DIFFERENTIAL SIGNALING TRANSMITTER AND TRANSMITTING METHOD' [patent_app_type] => utility [patent_app_number] => 12/032700 [patent_app_country] => US [patent_app_date] => 2008-02-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4417 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0116/20090116564.pdf [firstpage_image] =>[orig_patent_app_number] => 12032700 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/032700
Low voltage differential signaling transmitter and transmitting method Feb 17, 2008 Issued
Array ( [id] => 5434268 [patent_doc_number] => 20090168854 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-07-02 [patent_title] => 'De-Emphasis Circuit for a Voltage Mode Driver Used to Communicate Via a Differential Communication Link' [patent_app_type] => utility [patent_app_number] => 12/032741 [patent_app_country] => US [patent_app_date] => 2008-02-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4944 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0168/20090168854.pdf [firstpage_image] =>[orig_patent_app_number] => 12032741 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/032741
De-emphasis circuit for a voltage mode driver used to communicate via a differential communication link Feb 17, 2008 Issued
Array ( [id] => 5414030 [patent_doc_number] => 20090039917 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-02-12 [patent_title] => 'Programmable Interconnect Structures' [patent_app_type] => utility [patent_app_number] => 12/032667 [patent_app_country] => US [patent_app_date] => 2008-02-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 15165 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0039/20090039917.pdf [firstpage_image] =>[orig_patent_app_number] => 12032667 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/032667
Programmable interconnect structures Feb 15, 2008 Issued
Array ( [id] => 4724529 [patent_doc_number] => 20080204070 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-08-28 [patent_title] => 'Reduced power output buffer' [patent_app_type] => utility [patent_app_number] => 12/070374 [patent_app_country] => US [patent_app_date] => 2008-02-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3522 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0204/20080204070.pdf [firstpage_image] =>[orig_patent_app_number] => 12070374 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/070374
Reduced power output buffer Feb 14, 2008 Issued
Array ( [id] => 4458081 [patent_doc_number] => 07893721 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-02-22 [patent_title] => 'Dual rail domino circuit and logic circuit' [patent_app_type] => utility [patent_app_number] => 12/528572 [patent_app_country] => US [patent_app_date] => 2008-02-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 3707 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/893/07893721.pdf [firstpage_image] =>[orig_patent_app_number] => 12528572 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/528572
Dual rail domino circuit and logic circuit Feb 14, 2008 Issued
Array ( [id] => 45544 [patent_doc_number] => 07777520 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-08-17 [patent_title] => 'System, method and apparatus for enhancing reliability on scan-initialized latches affecting functionality' [patent_app_type] => utility [patent_app_number] => 12/031730 [patent_app_country] => US [patent_app_date] => 2008-02-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2878 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/777/07777520.pdf [firstpage_image] =>[orig_patent_app_number] => 12031730 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/031730
System, method and apparatus for enhancing reliability on scan-initialized latches affecting functionality Feb 14, 2008 Issued
Array ( [id] => 8578434 [patent_doc_number] => 08344649 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-01-01 [patent_title] => 'Universal electronic ballast for operating Hg-free lamps and Hg-containing discharge lamps' [patent_app_type] => utility [patent_app_number] => 12/527558 [patent_app_country] => US [patent_app_date] => 2008-02-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 3135 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 64 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12527558 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/527558
Universal electronic ballast for operating Hg-free lamps and Hg-containing discharge lamps Feb 11, 2008 Issued
Array ( [id] => 5282812 [patent_doc_number] => 20090096486 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-04-16 [patent_title] => 'Structure for Transmission Gate Multiplexer' [patent_app_type] => utility [patent_app_number] => 12/028940 [patent_app_country] => US [patent_app_date] => 2008-02-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3882 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0096/20090096486.pdf [firstpage_image] =>[orig_patent_app_number] => 12028940 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/028940
Structure for Transmission Gate Multiplexer Feb 10, 2008 Abandoned
Array ( [id] => 212037 [patent_doc_number] => 07622944 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-11-24 [patent_title] => 'Method to reduce power in active shield circuits that use complementary traces' [patent_app_type] => utility [patent_app_number] => 12/027494 [patent_app_country] => US [patent_app_date] => 2008-02-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 3710 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 58 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/622/07622944.pdf [firstpage_image] =>[orig_patent_app_number] => 12027494 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/027494
Method to reduce power in active shield circuits that use complementary traces Feb 6, 2008 Issued
Array ( [id] => 837520 [patent_doc_number] => 07394281 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2008-07-01 [patent_title] => 'Bi-directional universal serial bus booster circuit' [patent_app_type] => utility [patent_app_number] => 12/023659 [patent_app_country] => US [patent_app_date] => 2008-01-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 1969 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/394/07394281.pdf [firstpage_image] =>[orig_patent_app_number] => 12023659 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/023659
Bi-directional universal serial bus booster circuit Jan 30, 2008 Issued
Array ( [id] => 55370 [patent_doc_number] => 07768297 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-08-03 [patent_title] => 'Multi-drop bus system' [patent_app_type] => utility [patent_app_number] => 12/012511 [patent_app_country] => US [patent_app_date] => 2008-01-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 19 [patent_no_of_words] => 7097 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 52 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/768/07768297.pdf [firstpage_image] =>[orig_patent_app_number] => 12012511 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/012511
Multi-drop bus system Jan 30, 2008 Issued
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