Search

Don P. Le

Examiner (ID: 5300, Phone: (571)272-1806 , Office: P/2844 )

Most Active Art Unit
2819
Art Unit(s)
2844, 2819
Total Applications
2669
Issued Applications
2528
Pending Applications
46
Abandoned Applications
99

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 152831 [patent_doc_number] => 07683660 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2010-03-23 [patent_title] => 'Programmable logic device with a microcontroller-based control system' [patent_app_type] => utility [patent_app_number] => 12/023299 [patent_app_country] => US [patent_app_date] => 2008-01-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 9544 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/683/07683660.pdf [firstpage_image] =>[orig_patent_app_number] => 12023299 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/023299
Programmable logic device with a microcontroller-based control system Jan 30, 2008 Issued
Array ( [id] => 6305614 [patent_doc_number] => 20100109571 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-05-06 [patent_title] => 'INSULATION TYPE AC-DC CONVERTER AND LED DC POWER SUPPLY DEVICE USING THE SAME' [patent_app_type] => utility [patent_app_number] => 12/524640 [patent_app_country] => US [patent_app_date] => 2008-01-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 7738 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0109/20100109571.pdf [firstpage_image] =>[orig_patent_app_number] => 12524640 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/524640
Insulation type AC-DC converter and LED DC power supply device using the same Jan 29, 2008 Issued
Array ( [id] => 5377796 [patent_doc_number] => 20090189635 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-07-30 [patent_title] => 'METHOD AND APPARATUS FOR IMPLEMENTING REDUCED COUPLING EFFECTS ON SINGLE ENDED CLOCKS' [patent_app_type] => utility [patent_app_number] => 12/020727 [patent_app_country] => US [patent_app_date] => 2008-01-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 2806 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0189/20090189635.pdf [firstpage_image] =>[orig_patent_app_number] => 12020727 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/020727
METHOD AND APPARATUS FOR IMPLEMENTING REDUCED COUPLING EFFECTS ON SINGLE ENDED CLOCKS Jan 27, 2008 Abandoned
Array ( [id] => 5346670 [patent_doc_number] => 20090002031 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-01-01 [patent_title] => 'Slew rate controlled output driver for use in semiconductor device' [patent_app_type] => utility [patent_app_number] => 12/011420 [patent_app_country] => US [patent_app_date] => 2008-01-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 4714 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0002/20090002031.pdf [firstpage_image] =>[orig_patent_app_number] => 12011420 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/011420
Slew rate controlled output driver for use in semiconductor device Jan 24, 2008 Issued
Array ( [id] => 6257013 [patent_doc_number] => 20100295467 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-11-25 [patent_title] => 'CIRCUIT ARRANGEMENT AND METHOD FOR REGULATING THE CURRENT THROUGH AT LEAST ONE DISCHARGE LAMP' [patent_app_type] => utility [patent_app_number] => 12/864245 [patent_app_country] => US [patent_app_date] => 2008-01-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2279 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0295/20100295467.pdf [firstpage_image] =>[orig_patent_app_number] => 12864245 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/864245
Circuit arrangement and method for regulating the current through at least one discharge lamp Jan 23, 2008 Issued
Array ( [id] => 8738944 [patent_doc_number] => 08410719 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-04-02 [patent_title] => 'Electronic ballast and method for controlling at least one light source' [patent_app_type] => utility [patent_app_number] => 12/864253 [patent_app_country] => US [patent_app_date] => 2008-01-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 2851 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12864253 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/864253
Electronic ballast and method for controlling at least one light source Jan 23, 2008 Issued
Array ( [id] => 8410910 [patent_doc_number] => 08274309 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-09-25 [patent_title] => 'Programmable structured arrays' [patent_app_type] => utility [patent_app_number] => 12/018243 [patent_app_country] => US [patent_app_date] => 2008-01-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 39 [patent_no_of_words] => 14794 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 38 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12018243 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/018243
Programmable structured arrays Jan 22, 2008 Issued
Array ( [id] => 6604226 [patent_doc_number] => 20100033098 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-02-11 [patent_title] => 'METHOD AND DEVICE FOR DRIVING A GAS DISCHARGE LAMP' [patent_app_type] => utility [patent_app_number] => 12/524381 [patent_app_country] => US [patent_app_date] => 2008-01-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3481 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0033/20100033098.pdf [firstpage_image] =>[orig_patent_app_number] => 12524381 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/524381
Method and device for driving a gas discharge lamp Jan 22, 2008 Issued
Array ( [id] => 25301 [patent_doc_number] => 07795913 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-09-14 [patent_title] => 'Programmable latch based multiplier' [patent_app_type] => utility [patent_app_number] => 12/015461 [patent_app_country] => US [patent_app_date] => 2008-01-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 15 [patent_no_of_words] => 4054 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 52 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/795/07795913.pdf [firstpage_image] =>[orig_patent_app_number] => 12015461 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/015461
Programmable latch based multiplier Jan 15, 2008 Issued
Array ( [id] => 5341030 [patent_doc_number] => 20090179680 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-07-16 [patent_title] => 'METHOD AND APPARATUS FOR IMPLEMENTING BALANCED CLOCK DISTRIBUTION NETWORKS ON ASICS WITH VOLTAGE ISLANDS FUNCTIONING AT MULTIPLE OPERATING POINTS OF VOLTAGE AND TEMPERATURE' [patent_app_type] => utility [patent_app_number] => 12/014172 [patent_app_country] => US [patent_app_date] => 2008-01-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3310 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0179/20090179680.pdf [firstpage_image] =>[orig_patent_app_number] => 12014172 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/014172
Method and apparatus for implementing balanced clock distribution networks on ASICs with voltage islands functioning at multiple operating points of voltage and temperature Jan 14, 2008 Issued
Array ( [id] => 799212 [patent_doc_number] => 07428722 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-09-23 [patent_title] => 'Versatile multiplexer-structures in programmable logic using serial chaining and novel selection schemes' [patent_app_type] => utility [patent_app_number] => 12/007705 [patent_app_country] => US [patent_app_date] => 2008-01-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 15 [patent_no_of_words] => 2618 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 50 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/428/07428722.pdf [firstpage_image] =>[orig_patent_app_number] => 12007705 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/007705
Versatile multiplexer-structures in programmable logic using serial chaining and novel selection schemes Jan 14, 2008 Issued
Array ( [id] => 233337 [patent_doc_number] => 07598766 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-10-06 [patent_title] => 'Customized silicon chips produced using dynamically configurable polymorphic network' [patent_app_type] => utility [patent_app_number] => 11/971349 [patent_app_country] => US [patent_app_date] => 2008-01-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 17 [patent_no_of_words] => 16750 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/598/07598766.pdf [firstpage_image] =>[orig_patent_app_number] => 11971349 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/971349
Customized silicon chips produced using dynamically configurable polymorphic network Jan 8, 2008 Issued
Array ( [id] => 311598 [patent_doc_number] => 07528630 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-05-05 [patent_title] => 'High speed flip-flop' [patent_app_type] => utility [patent_app_number] => 11/970629 [patent_app_country] => US [patent_app_date] => 2008-01-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 2718 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/528/07528630.pdf [firstpage_image] =>[orig_patent_app_number] => 11970629 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/970629
High speed flip-flop Jan 7, 2008 Issued
Array ( [id] => 4749741 [patent_doc_number] => 20080157812 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-07-03 [patent_title] => 'CHIP WITH IN-CIRCUIT PROGRAMABILITY' [patent_app_type] => utility [patent_app_number] => 11/968294 [patent_app_country] => US [patent_app_date] => 2008-01-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2066 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0157/20080157812.pdf [firstpage_image] =>[orig_patent_app_number] => 11968294 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/968294
Chip with in-circuit programability Jan 1, 2008 Issued
Array ( [id] => 4497100 [patent_doc_number] => 07956640 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-06-07 [patent_title] => 'Digital radio frequency switch matrix' [patent_app_type] => utility [patent_app_number] => 11/966918 [patent_app_country] => US [patent_app_date] => 2007-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 14 [patent_no_of_words] => 3501 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/956/07956640.pdf [firstpage_image] =>[orig_patent_app_number] => 11966918 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/966918
Digital radio frequency switch matrix Dec 27, 2007 Issued
Array ( [id] => 4902170 [patent_doc_number] => 20080111583 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-05-15 [patent_title] => 'IMPLEMENTING LOGIC FUNCTIONS WITH NON-MAGNITUDE BASED PHYSICAL PHENOMENA' [patent_app_type] => utility [patent_app_number] => 11/964507 [patent_app_country] => US [patent_app_date] => 2007-12-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 14609 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0111/20080111583.pdf [firstpage_image] =>[orig_patent_app_number] => 11964507 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/964507
Implementing logic functions with non-magnitude based physical phenomena Dec 25, 2007 Issued
Array ( [id] => 229398 [patent_doc_number] => 07602213 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-10-13 [patent_title] => 'Using programmable latch to implement logic' [patent_app_type] => utility [patent_app_number] => 11/964084 [patent_app_country] => US [patent_app_date] => 2007-12-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 2744 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 49 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/602/07602213.pdf [firstpage_image] =>[orig_patent_app_number] => 11964084 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/964084
Using programmable latch to implement logic Dec 25, 2007 Issued
Array ( [id] => 185955 [patent_doc_number] => 07649379 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-01-19 [patent_title] => 'Reducing mission signal output delay in IC having mission and test modes' [patent_app_type] => utility [patent_app_number] => 11/964323 [patent_app_country] => US [patent_app_date] => 2007-12-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 1726 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/649/07649379.pdf [firstpage_image] =>[orig_patent_app_number] => 11964323 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/964323
Reducing mission signal output delay in IC having mission and test modes Dec 25, 2007 Issued
Array ( [id] => 4913501 [patent_doc_number] => 20080094100 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-04-24 [patent_title] => 'ADJUSTABLE TRANSISTOR BODY BIAS GENERATION CIRCUITRY WITH LATCH-UP PREVENTION' [patent_app_type] => utility [patent_app_number] => 11/959949 [patent_app_country] => US [patent_app_date] => 2007-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 9789 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0094/20080094100.pdf [firstpage_image] =>[orig_patent_app_number] => 11959949 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/959949
Adjustable transistor body bias generation circuitry with latch-up prevention Dec 18, 2007 Issued
Array ( [id] => 353159 [patent_doc_number] => 07492185 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2009-02-17 [patent_title] => 'Innovated technique to reduce memory interface write mode SSN in FPGA' [patent_app_type] => utility [patent_app_number] => 11/956182 [patent_app_country] => US [patent_app_date] => 2007-12-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4864 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/492/07492185.pdf [firstpage_image] =>[orig_patent_app_number] => 11956182 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/956182
Innovated technique to reduce memory interface write mode SSN in FPGA Dec 12, 2007 Issued
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