Search

Don P. Le

Examiner (ID: 5300, Phone: (571)272-1806 , Office: P/2844 )

Most Active Art Unit
2819
Art Unit(s)
2844, 2819
Total Applications
2669
Issued Applications
2528
Pending Applications
46
Abandoned Applications
99

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 5262767 [patent_doc_number] => 20090115452 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-05-07 [patent_title] => 'LOGIC BLOCK CONTROL SYSTEM AND LOGIC BLOCK CONTROL METHOD' [patent_app_type] => utility [patent_app_number] => 12/093263 [patent_app_country] => US [patent_app_date] => 2006-11-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 10265 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0115/20090115452.pdf [firstpage_image] =>[orig_patent_app_number] => 12093263 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/093263
Logic block control system and logic block control method Nov 14, 2006 Issued
Array ( [id] => 853734 [patent_doc_number] => 07378868 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-05-27 [patent_title] => 'Modular I/O bank architecture' [patent_app_type] => utility [patent_app_number] => 11/558363 [patent_app_country] => US [patent_app_date] => 2006-11-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 6059 [patent_no_of_claims] => 40 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/378/07378868.pdf [firstpage_image] =>[orig_patent_app_number] => 11558363 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/558363
Modular I/O bank architecture Nov 8, 2006 Issued
Array ( [id] => 5181102 [patent_doc_number] => 20070052444 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-03-08 [patent_title] => 'Programmable interconnect structures' [patent_app_type] => utility [patent_app_number] => 11/593182 [patent_app_country] => US [patent_app_date] => 2006-11-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 15110 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0052/20070052444.pdf [firstpage_image] =>[orig_patent_app_number] => 11593182 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/593182
Programmable interconnect structures Nov 5, 2006 Issued
Array ( [id] => 5054770 [patent_doc_number] => 20070057691 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-03-15 [patent_title] => 'Output Driver Circuit' [patent_app_type] => utility [patent_app_number] => 11/556056 [patent_app_country] => US [patent_app_date] => 2006-11-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4372 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0057/20070057691.pdf [firstpage_image] =>[orig_patent_app_number] => 11556056 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/556056
Output driver circuit Nov 1, 2006 Issued
Array ( [id] => 594162 [patent_doc_number] => 07436209 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2008-10-14 [patent_title] => 'Nanoscale electronic latch' [patent_app_type] => utility [patent_app_number] => 11/590491 [patent_app_country] => US [patent_app_date] => 2006-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 25 [patent_no_of_words] => 4457 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/436/07436209.pdf [firstpage_image] =>[orig_patent_app_number] => 11590491 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/590491
Nanoscale electronic latch Oct 29, 2006 Issued
Array ( [id] => 4997940 [patent_doc_number] => 20070040574 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-02-22 [patent_title] => 'Apparatus and method for independent control of on-die termination for output buffers of a memory device' [patent_app_type] => utility [patent_app_number] => 11/588473 [patent_app_country] => US [patent_app_date] => 2006-10-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 8145 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0040/20070040574.pdf [firstpage_image] =>[orig_patent_app_number] => 11588473 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/588473
Apparatus and method for independent control of on-die termination for output buffers of a memory device Oct 25, 2006 Issued
Array ( [id] => 409100 [patent_doc_number] => 07285983 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-10-23 [patent_title] => 'Programmable array logic circuit employing non-volatile ferromagnetic memory cells' [patent_app_type] => utility [patent_app_number] => 11/580064 [patent_app_country] => US [patent_app_date] => 2006-10-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2201 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/285/07285983.pdf [firstpage_image] =>[orig_patent_app_number] => 11580064 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/580064
Programmable array logic circuit employing non-volatile ferromagnetic memory cells Oct 12, 2006 Issued
Array ( [id] => 465866 [patent_doc_number] => 07239175 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-07-03 [patent_title] => 'Look-up table based logic macro-cells' [patent_app_type] => utility [patent_app_number] => 11/546681 [patent_app_country] => US [patent_app_date] => 2006-10-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 50 [patent_no_of_words] => 17501 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/239/07239175.pdf [firstpage_image] =>[orig_patent_app_number] => 11546681 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/546681
Look-up table based logic macro-cells Oct 12, 2006 Issued
Array ( [id] => 465864 [patent_doc_number] => 07239174 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-07-03 [patent_title] => 'Programmable interconnect structures' [patent_app_type] => utility [patent_app_number] => 11/545044 [patent_app_country] => US [patent_app_date] => 2006-10-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 40 [patent_no_of_words] => 14620 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/239/07239174.pdf [firstpage_image] =>[orig_patent_app_number] => 11545044 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/545044
Programmable interconnect structures Oct 9, 2006 Issued
Array ( [id] => 803747 [patent_doc_number] => 07423454 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-09-09 [patent_title] => 'High speed signaling system with adaptive transmit pre-emphasis' [patent_app_type] => utility [patent_app_number] => 11/538333 [patent_app_country] => US [patent_app_date] => 2006-10-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 33 [patent_no_of_words] => 33386 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/423/07423454.pdf [firstpage_image] =>[orig_patent_app_number] => 11538333 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/538333
High speed signaling system with adaptive transmit pre-emphasis Oct 2, 2006 Issued
Array ( [id] => 873747 [patent_doc_number] => 07362132 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-04-22 [patent_title] => 'Reconfigurable integrated circuit device to automatically configure an initialization circuit' [patent_app_type] => utility [patent_app_number] => 11/524386 [patent_app_country] => US [patent_app_date] => 2006-09-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5680 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/362/07362132.pdf [firstpage_image] =>[orig_patent_app_number] => 11524386 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/524386
Reconfigurable integrated circuit device to automatically configure an initialization circuit Sep 20, 2006 Issued
Array ( [id] => 5214176 [patent_doc_number] => 20070103256 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-05-10 [patent_title] => 'Low-pass filter capable of preventing unnecessary electromagnetic coupling' [patent_app_type] => utility [patent_app_number] => 11/521756 [patent_app_country] => US [patent_app_date] => 2006-09-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4607 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0103/20070103256.pdf [firstpage_image] =>[orig_patent_app_number] => 11521756 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/521756
Low-pass filter capable of preventing unnecessary electromagnetic coupling Sep 14, 2006 Issued
Array ( [id] => 345710 [patent_doc_number] => 07498900 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-03-03 [patent_title] => 'System on chip structure comprising air cavity for isolating elements, duplexer, and duplexer fabrication method thereof' [patent_app_type] => utility [patent_app_number] => 11/517371 [patent_app_country] => US [patent_app_date] => 2006-09-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 3942 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/498/07498900.pdf [firstpage_image] =>[orig_patent_app_number] => 11517371 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/517371
System on chip structure comprising air cavity for isolating elements, duplexer, and duplexer fabrication method thereof Sep 7, 2006 Issued
Array ( [id] => 5038618 [patent_doc_number] => 20070090900 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-04-26 [patent_title] => 'BAND-PASS FILTER' [patent_app_type] => utility [patent_app_number] => 11/309627 [patent_app_country] => US [patent_app_date] => 2006-09-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 1907 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0090/20070090900.pdf [firstpage_image] =>[orig_patent_app_number] => 11309627 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/309627
Band-pass filter Aug 31, 2006 Issued
Array ( [id] => 4769362 [patent_doc_number] => 20080055020 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-03-06 [patent_title] => 'Acoustic Resonator' [patent_app_type] => utility [patent_app_number] => 11/513895 [patent_app_country] => US [patent_app_date] => 2006-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 8148 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0055/20080055020.pdf [firstpage_image] =>[orig_patent_app_number] => 11513895 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/513895
Acoustic resonator Aug 30, 2006 Issued
Array ( [id] => 814154 [patent_doc_number] => 07414430 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-08-19 [patent_title] => 'Programmable logic device having an embedded differential clock tree' [patent_app_type] => utility [patent_app_number] => 11/511647 [patent_app_country] => US [patent_app_date] => 2006-08-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 32 [patent_figures_cnt] => 32 [patent_no_of_words] => 17366 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/414/07414430.pdf [firstpage_image] =>[orig_patent_app_number] => 11511647 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/511647
Programmable logic device having an embedded differential clock tree Aug 28, 2006 Issued
Array ( [id] => 861726 [patent_doc_number] => 07372299 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-05-13 [patent_title] => 'Differential clock tree in an integrated circuit' [patent_app_type] => utility [patent_app_number] => 11/511779 [patent_app_country] => US [patent_app_date] => 2006-08-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 32 [patent_figures_cnt] => 32 [patent_no_of_words] => 17335 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 56 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/372/07372299.pdf [firstpage_image] =>[orig_patent_app_number] => 11511779 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/511779
Differential clock tree in an integrated circuit Aug 28, 2006 Issued
Array ( [id] => 383493 [patent_doc_number] => 07307445 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-12-11 [patent_title] => 'Apparatus and methods for multi-gate silicon-on-insulator transistors' [patent_app_type] => utility [patent_app_number] => 11/466565 [patent_app_country] => US [patent_app_date] => 2006-08-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 23 [patent_no_of_words] => 10147 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/307/07307445.pdf [firstpage_image] =>[orig_patent_app_number] => 11466565 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/466565
Apparatus and methods for multi-gate silicon-on-insulator transistors Aug 22, 2006 Issued
Array ( [id] => 349406 [patent_doc_number] => 07495525 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-02-24 [patent_title] => 'Multilayer planar balun transformer, mixers and amplifiers' [patent_app_type] => utility [patent_app_number] => 11/507868 [patent_app_country] => US [patent_app_date] => 2006-08-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 18 [patent_no_of_words] => 5045 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/495/07495525.pdf [firstpage_image] =>[orig_patent_app_number] => 11507868 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/507868
Multilayer planar balun transformer, mixers and amplifiers Aug 21, 2006 Issued
Array ( [id] => 814152 [patent_doc_number] => 07414428 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-08-19 [patent_title] => 'Non-volatile memory configuration scheme for volatile-memory-based programmable circuits in an FPGA' [patent_app_type] => utility [patent_app_number] => 11/465899 [patent_app_country] => US [patent_app_date] => 2006-08-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2133 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 146 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/414/07414428.pdf [firstpage_image] =>[orig_patent_app_number] => 11465899 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/465899
Non-volatile memory configuration scheme for volatile-memory-based programmable circuits in an FPGA Aug 20, 2006 Issued
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