Search

Don P. Le

Examiner (ID: 5300, Phone: (571)272-1806 , Office: P/2844 )

Most Active Art Unit
2819
Art Unit(s)
2844, 2819
Total Applications
2669
Issued Applications
2528
Pending Applications
46
Abandoned Applications
99

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 5674062 [patent_doc_number] => 20060179417 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-08-10 [patent_title] => 'Alterable application specific integrated circuit (ASIC)' [patent_app_type] => utility [patent_app_number] => 11/400122 [patent_app_country] => US [patent_app_date] => 2006-04-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 10180 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0179/20060179417.pdf [firstpage_image] =>[orig_patent_app_number] => 11400122 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/400122
Alterable application specific integrated circuit (ASIC) Apr 9, 2006 Issued
Array ( [id] => 594233 [patent_doc_number] => 07436220 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-10-14 [patent_title] => 'Partially gated mux-latch keeper' [patent_app_type] => utility [patent_app_number] => 11/394545 [patent_app_country] => US [patent_app_date] => 2006-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3201 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 38 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/436/07436220.pdf [firstpage_image] =>[orig_patent_app_number] => 11394545 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/394545
Partially gated mux-latch keeper Mar 30, 2006 Issued
Array ( [id] => 5123950 [patent_doc_number] => 20070236220 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-10-11 [patent_title] => 'Apparatus to receive signals from electromagnetic coupler' [patent_app_type] => utility [patent_app_number] => 11/394207 [patent_app_country] => US [patent_app_date] => 2006-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5066 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0236/20070236220.pdf [firstpage_image] =>[orig_patent_app_number] => 11394207 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/394207
Apparatus to receive signals from electromagnetic coupler Mar 30, 2006 Issued
Array ( [id] => 514299 [patent_doc_number] => 07196544 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-03-27 [patent_title] => 'Communication device for a logic circuit' [patent_app_type] => utility [patent_app_number] => 11/394256 [patent_app_country] => US [patent_app_date] => 2006-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 13 [patent_no_of_words] => 4152 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 59 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/196/07196544.pdf [firstpage_image] =>[orig_patent_app_number] => 11394256 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/394256
Communication device for a logic circuit Mar 29, 2006 Issued
Array ( [id] => 5120150 [patent_doc_number] => 20070141865 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-06-21 [patent_title] => 'APPARATUS FOR EXPRESSING CIRCUIT VERSION IDENTIFICATION INFORMATION' [patent_app_type] => utility [patent_app_number] => 11/308490 [patent_app_country] => US [patent_app_date] => 2006-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2882 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0141/20070141865.pdf [firstpage_image] =>[orig_patent_app_number] => 11308490 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/308490
Apparatus for expressing circuit version identification information Mar 29, 2006 Issued
Array ( [id] => 513762 [patent_doc_number] => 07199615 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-04-03 [patent_title] => 'High speed signaling system with adaptive transmit pre-emphasis and reflection cancellation' [patent_app_type] => utility [patent_app_number] => 11/386984 [patent_app_country] => US [patent_app_date] => 2006-03-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 38 [patent_figures_cnt] => 63 [patent_no_of_words] => 54413 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/199/07199615.pdf [firstpage_image] =>[orig_patent_app_number] => 11386984 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/386984
High speed signaling system with adaptive transmit pre-emphasis and reflection cancellation Mar 20, 2006 Issued
Array ( [id] => 5129405 [patent_doc_number] => 20070205802 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-09-06 [patent_title] => 'ADJUSTABLE TRANSISTOR BODY BIAS GENERATION CIRCUITRY WITH LATCH-UP PREVENTION' [patent_app_type] => utility [patent_app_number] => 11/369548 [patent_app_country] => US [patent_app_date] => 2006-03-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 9762 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0205/20070205802.pdf [firstpage_image] =>[orig_patent_app_number] => 11369548 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/369548
Adjustable transistor body bias generation circuitry with latch-up prevention Mar 5, 2006 Issued
Array ( [id] => 409099 [patent_doc_number] => 07285982 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-10-23 [patent_title] => 'Configuration circuits for programmable logic devices' [patent_app_type] => utility [patent_app_number] => 11/365031 [patent_app_country] => US [patent_app_date] => 2006-03-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 17 [patent_no_of_words] => 7059 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/285/07285982.pdf [firstpage_image] =>[orig_patent_app_number] => 11365031 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/365031
Configuration circuits for programmable logic devices Mar 1, 2006 Issued
Array ( [id] => 331034 [patent_doc_number] => 07511533 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2009-03-31 [patent_title] => 'Output device having parasitic transistor for increased current drive' [patent_app_type] => utility [patent_app_number] => 11/364779 [patent_app_country] => US [patent_app_date] => 2006-02-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 11 [patent_no_of_words] => 4716 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 64 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/511/07511533.pdf [firstpage_image] =>[orig_patent_app_number] => 11364779 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/364779
Output device having parasitic transistor for increased current drive Feb 26, 2006 Issued
Array ( [id] => 881623 [patent_doc_number] => 07355441 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2008-04-08 [patent_title] => 'Programmable logic devices with distributed memory and non-volatile memory' [patent_app_type] => utility [patent_app_number] => 11/360337 [patent_app_country] => US [patent_app_date] => 2006-02-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 11 [patent_no_of_words] => 3152 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/355/07355441.pdf [firstpage_image] =>[orig_patent_app_number] => 11360337 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/360337
Programmable logic devices with distributed memory and non-volatile memory Feb 21, 2006 Issued
Array ( [id] => 5653316 [patent_doc_number] => 20060139051 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-06-29 [patent_title] => 'Variable impedence output buffer' [patent_app_type] => utility [patent_app_number] => 11/358235 [patent_app_country] => US [patent_app_date] => 2006-02-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3568 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0139/20060139051.pdf [firstpage_image] =>[orig_patent_app_number] => 11358235 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/358235
Variable impedence output buffer Feb 20, 2006 Issued
Array ( [id] => 409098 [patent_doc_number] => 07285981 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-10-23 [patent_title] => 'Configuration circuit for programmable logic devices' [patent_app_type] => utility [patent_app_number] => 11/357145 [patent_app_country] => US [patent_app_date] => 2006-02-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 19 [patent_no_of_words] => 8216 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/285/07285981.pdf [firstpage_image] =>[orig_patent_app_number] => 11357145 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/357145
Configuration circuit for programmable logic devices Feb 20, 2006 Issued
Array ( [id] => 197860 [patent_doc_number] => 07639044 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-12-29 [patent_title] => 'Semiconductor integrated circuit, semiconductor integrated circuit control method, and signal transmission circuit' [patent_app_type] => utility [patent_app_number] => 11/814691 [patent_app_country] => US [patent_app_date] => 2006-02-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 6755 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/639/07639044.pdf [firstpage_image] =>[orig_patent_app_number] => 11814691 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/814691
Semiconductor integrated circuit, semiconductor integrated circuit control method, and signal transmission circuit Feb 16, 2006 Issued
Array ( [id] => 5653321 [patent_doc_number] => 20060139056 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-06-29 [patent_title] => 'Field programmable structured arrays' [patent_app_type] => utility [patent_app_number] => 11/355930 [patent_app_country] => US [patent_app_date] => 2006-02-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 14714 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0139/20060139056.pdf [firstpage_image] =>[orig_patent_app_number] => 11355930 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/355930
Field programmable structured arrays Feb 16, 2006 Issued
Array ( [id] => 5653319 [patent_doc_number] => 20060139054 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-06-29 [patent_title] => 'Look-up table structure with embedded carry logic' [patent_app_type] => utility [patent_app_number] => 11/355931 [patent_app_country] => US [patent_app_date] => 2006-02-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 20191 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0139/20060139054.pdf [firstpage_image] =>[orig_patent_app_number] => 11355931 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/355931
Look-up table structure with embedded carry logic Feb 16, 2006 Issued
Array ( [id] => 5003075 [patent_doc_number] => 20070200642 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-08-30 [patent_title] => 'Clock translator and parallel to serial converter' [patent_app_type] => utility [patent_app_number] => 11/356227 [patent_app_country] => US [patent_app_date] => 2006-02-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2758 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0200/20070200642.pdf [firstpage_image] =>[orig_patent_app_number] => 11356227 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/356227
Clock translator and parallel to serial converter Feb 15, 2006 Issued
Array ( [id] => 5621220 [patent_doc_number] => 20060190755 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-08-24 [patent_title] => 'System-on-chip having adjustable voltage level and method for the same' [patent_app_type] => utility [patent_app_number] => 11/355001 [patent_app_country] => US [patent_app_date] => 2006-02-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3771 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0190/20060190755.pdf [firstpage_image] =>[orig_patent_app_number] => 11355001 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/355001
System-on-chip having adjustable voltage level and method for the same Feb 15, 2006 Issued
Array ( [id] => 911768 [patent_doc_number] => 07330051 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2008-02-12 [patent_title] => 'Innovated technique to reduce memory interface write mode SSN in FPGA' [patent_app_type] => utility [patent_app_number] => 11/354766 [patent_app_country] => US [patent_app_date] => 2006-02-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4809 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/330/07330051.pdf [firstpage_image] =>[orig_patent_app_number] => 11354766 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/354766
Innovated technique to reduce memory interface write mode SSN in FPGA Feb 13, 2006 Issued
Array ( [id] => 549092 [patent_doc_number] => 07167018 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2007-01-23 [patent_title] => 'Circuits, architectures, systems and methods for overvoltage protection' [patent_app_type] => utility [patent_app_number] => 11/353736 [patent_app_country] => US [patent_app_date] => 2006-02-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 4791 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/167/07167018.pdf [firstpage_image] =>[orig_patent_app_number] => 11353736 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/353736
Circuits, architectures, systems and methods for overvoltage protection Feb 12, 2006 Issued
Array ( [id] => 5646443 [patent_doc_number] => 20060132175 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-06-22 [patent_title] => 'Look-up table based logic macro-cells' [patent_app_type] => utility [patent_app_number] => 11/350628 [patent_app_country] => US [patent_app_date] => 2006-02-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 17440 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0132/20060132175.pdf [firstpage_image] =>[orig_patent_app_number] => 11350628 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/350628
Look-up table based logic macro-cells Feb 9, 2006 Issued
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