Search

Don P. Le

Examiner (ID: 5300, Phone: (571)272-1806 , Office: P/2844 )

Most Active Art Unit
2819
Art Unit(s)
2844, 2819
Total Applications
2669
Issued Applications
2528
Pending Applications
46
Abandoned Applications
99

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 575940 [patent_doc_number] => 07463056 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2008-12-09 [patent_title] => 'Writeable shift register lookup table in FPGA with SRAM memory cells in lookup table reprogrammed by writing after initial configuration' [patent_app_type] => utility [patent_app_number] => 11/301056 [patent_app_country] => US [patent_app_date] => 2005-12-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 10 [patent_no_of_words] => 3027 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 55 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/463/07463056.pdf [firstpage_image] =>[orig_patent_app_number] => 11301056 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/301056
Writeable shift register lookup table in FPGA with SRAM memory cells in lookup table reprogrammed by writing after initial configuration Dec 11, 2005 Issued
Array ( [id] => 5909811 [patent_doc_number] => 20060125519 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-06-15 [patent_title] => 'Programmable logic array' [patent_app_type] => utility [patent_app_number] => 11/295634 [patent_app_country] => US [patent_app_date] => 2005-12-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4096 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0125/20060125519.pdf [firstpage_image] =>[orig_patent_app_number] => 11295634 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/295634
Programmable logic array Dec 6, 2005 Issued
Array ( [id] => 5730719 [patent_doc_number] => 20060255833 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-11-16 [patent_title] => 'FPGA device and method for rapid interconnect and logic testing of the same' [patent_app_type] => utility [patent_app_number] => 11/294645 [patent_app_country] => US [patent_app_date] => 2005-12-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2069 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0255/20060255833.pdf [firstpage_image] =>[orig_patent_app_number] => 11294645 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/294645
Rapid interconnect and logic testing of FPGA device Dec 4, 2005 Issued
Array ( [id] => 5652865 [patent_doc_number] => 20060138600 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-06-29 [patent_title] => 'Unit circuit, method of controlling unit circuit, electronic device, and electronic apparatus' [patent_app_type] => utility [patent_app_number] => 11/290581 [patent_app_country] => US [patent_app_date] => 2005-12-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 10180 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0138/20060138600.pdf [firstpage_image] =>[orig_patent_app_number] => 11290581 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/290581
Unit circuit, method of controlling unit circuit, electronic device, and electronic apparatus Nov 30, 2005 Issued
Array ( [id] => 5838884 [patent_doc_number] => 20060119378 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-06-08 [patent_title] => 'Apparatus and method for protecting from illegal copy' [patent_app_type] => utility [patent_app_number] => 11/290396 [patent_app_country] => US [patent_app_date] => 2005-12-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6158 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0119/20060119378.pdf [firstpage_image] =>[orig_patent_app_number] => 11290396 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/290396
Apparatus and method for protecting from illegal copy Nov 30, 2005 Issued
Array ( [id] => 356722 [patent_doc_number] => 07489162 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2009-02-10 [patent_title] => 'Users registers in a reconfigurable IC' [patent_app_type] => utility [patent_app_number] => 11/293856 [patent_app_country] => US [patent_app_date] => 2005-12-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 36 [patent_no_of_words] => 9707 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/489/07489162.pdf [firstpage_image] =>[orig_patent_app_number] => 11293856 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/293856
Users registers in a reconfigurable IC Nov 30, 2005 Issued
Array ( [id] => 918681 [patent_doc_number] => 07323907 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2008-01-29 [patent_title] => 'Pre-emphasis driver control' [patent_app_type] => utility [patent_app_number] => 11/292228 [patent_app_country] => US [patent_app_date] => 2005-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5024 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/323/07323907.pdf [firstpage_image] =>[orig_patent_app_number] => 11292228 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/292228
Pre-emphasis driver control Nov 29, 2005 Issued
Array ( [id] => 398212 [patent_doc_number] => 07295036 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2007-11-13 [patent_title] => 'Method and system for reducing static leakage current in programmable logic devices' [patent_app_type] => utility [patent_app_number] => 11/291712 [patent_app_country] => US [patent_app_date] => 2005-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 17 [patent_no_of_words] => 6557 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 31 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/295/07295036.pdf [firstpage_image] =>[orig_patent_app_number] => 11291712 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/291712
Method and system for reducing static leakage current in programmable logic devices Nov 29, 2005 Issued
Array ( [id] => 377526 [patent_doc_number] => 07312628 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-12-25 [patent_title] => 'Method and apparatus for CAN bus auto-termination' [patent_app_type] => utility [patent_app_number] => 11/288616 [patent_app_country] => US [patent_app_date] => 2005-11-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 2864 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 49 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/312/07312628.pdf [firstpage_image] =>[orig_patent_app_number] => 11288616 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/288616
Method and apparatus for CAN bus auto-termination Nov 28, 2005 Issued
Array ( [id] => 5646450 [patent_doc_number] => 20060132182 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-06-22 [patent_title] => 'Driver circuit, shift register, and liquid crystal driver circuit' [patent_app_type] => utility [patent_app_number] => 11/289829 [patent_app_country] => US [patent_app_date] => 2005-11-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 6909 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0132/20060132182.pdf [firstpage_image] =>[orig_patent_app_number] => 11289829 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/289829
Driver circuit, shift register, and liquid crystal driver circuit Nov 28, 2005 Abandoned
Array ( [id] => 915678 [patent_doc_number] => 07327159 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2008-02-05 [patent_title] => 'Interface block architectures' [patent_app_type] => utility [patent_app_number] => 11/287720 [patent_app_country] => US [patent_app_date] => 2005-11-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 3564 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/327/07327159.pdf [firstpage_image] =>[orig_patent_app_number] => 11287720 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/287720
Interface block architectures Nov 27, 2005 Issued
Array ( [id] => 387137 [patent_doc_number] => 07304507 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2007-12-04 [patent_title] => 'Modular buffering circuitry for multi-channel transceiver clock and other signals' [patent_app_type] => utility [patent_app_number] => 11/288496 [patent_app_country] => US [patent_app_date] => 2005-11-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 2970 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/304/07304507.pdf [firstpage_image] =>[orig_patent_app_number] => 11288496 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/288496
Modular buffering circuitry for multi-channel transceiver clock and other signals Nov 27, 2005 Issued
Array ( [id] => 5698217 [patent_doc_number] => 20060214901 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-09-28 [patent_title] => 'Semiconductor circuit, display device, electronic apparatus' [patent_app_type] => utility [patent_app_number] => 11/287957 [patent_app_country] => US [patent_app_date] => 2005-11-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 24 [patent_no_of_words] => 19685 [patent_no_of_claims] => 42 [patent_no_of_ind_claims] => 12 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0214/20060214901.pdf [firstpage_image] =>[orig_patent_app_number] => 11287957 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/287957
Semiconductor circuit, display device, electronic apparatus Nov 27, 2005 Issued
Array ( [id] => 5093421 [patent_doc_number] => 20070115030 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-05-24 [patent_title] => 'Differential buffer circuit with reduced output common mode variation' [patent_app_type] => utility [patent_app_number] => 11/285800 [patent_app_country] => US [patent_app_date] => 2005-11-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 7881 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0115/20070115030.pdf [firstpage_image] =>[orig_patent_app_number] => 11285800 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/285800
Differential buffer circuit with reduced output common mode variation Nov 22, 2005 Issued
Array ( [id] => 837541 [patent_doc_number] => 07394293 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2008-07-01 [patent_title] => 'Circuit and method for rapid power up of a differential output driver' [patent_app_type] => utility [patent_app_number] => 11/286764 [patent_app_country] => US [patent_app_date] => 2005-11-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5179 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 65 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/394/07394293.pdf [firstpage_image] =>[orig_patent_app_number] => 11286764 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/286764
Circuit and method for rapid power up of a differential output driver Nov 22, 2005 Issued
Array ( [id] => 429144 [patent_doc_number] => 07268582 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2007-09-11 [patent_title] => 'DPRIO for embedded hard IP' [patent_app_type] => utility [patent_app_number] => 11/286038 [patent_app_country] => US [patent_app_date] => 2005-11-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3265 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 60 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/268/07268582.pdf [firstpage_image] =>[orig_patent_app_number] => 11286038 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/286038
DPRIO for embedded hard IP Nov 21, 2005 Issued
Array ( [id] => 5635445 [patent_doc_number] => 20060066418 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-03-30 [patent_title] => 'Multi-section coupler assembly' [patent_app_type] => utility [patent_app_number] => 11/282197 [patent_app_country] => US [patent_app_date] => 2005-11-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5484 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0066/20060066418.pdf [firstpage_image] =>[orig_patent_app_number] => 11282197 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/282197
Multi-section coupler assembly Nov 16, 2005 Issued
Array ( [id] => 861715 [patent_doc_number] => 07372296 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-05-13 [patent_title] => 'Configurable logic device providing enhanced flexibility, scalability and providing area efficient implementation of arithmetic operation on n-bit variables' [patent_app_type] => utility [patent_app_number] => 11/263386 [patent_app_country] => US [patent_app_date] => 2005-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 18 [patent_no_of_words] => 6093 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/372/07372296.pdf [firstpage_image] =>[orig_patent_app_number] => 11263386 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/263386
Configurable logic device providing enhanced flexibility, scalability and providing area efficient implementation of arithmetic operation on n-bit variables Oct 30, 2005 Issued
Array ( [id] => 300378 [patent_doc_number] => 07538582 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-05-26 [patent_title] => 'Driver circuit, test apparatus and adjusting method' [patent_app_type] => utility [patent_app_number] => 11/262507 [patent_app_country] => US [patent_app_date] => 2005-10-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 13 [patent_no_of_words] => 6479 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/538/07538582.pdf [firstpage_image] =>[orig_patent_app_number] => 11262507 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/262507
Driver circuit, test apparatus and adjusting method Oct 27, 2005 Issued
Array ( [id] => 810748 [patent_doc_number] => 07417451 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-08-26 [patent_title] => 'Leakage power management with NDR isolation devices' [patent_app_type] => utility [patent_app_number] => 11/245933 [patent_app_country] => US [patent_app_date] => 2005-10-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3654 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 46 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/417/07417451.pdf [firstpage_image] =>[orig_patent_app_number] => 11245933 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/245933
Leakage power management with NDR isolation devices Oct 6, 2005 Issued
Menu