| Application number | Title of the application | Filing Date | Status |
|---|
Array
(
[id] => 3775895
[patent_doc_number] => 05773861
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-06-30
[patent_title] => 'Single transistor E.sup.2 PROM memory device'
[patent_app_type] => 1
[patent_app_number] => 8/559800
[patent_app_country] => US
[patent_app_date] => 1995-11-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 16
[patent_figures_cnt] => 32
[patent_no_of_words] => 6377
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 244
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/773/05773861.pdf
[firstpage_image] =>[orig_patent_app_number] => 559800
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/559800 | Single transistor E.sup.2 PROM memory device | Nov 16, 1995 | Issued |
Array
(
[id] => 3638237
[patent_doc_number] => 05610434
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-03-11
[patent_title] => 'Mesa semiconductor structure'
[patent_app_type] => 1
[patent_app_number] => 8/554749
[patent_app_country] => US
[patent_app_date] => 1995-11-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 10
[patent_no_of_words] => 4297
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 60
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/610/05610434.pdf
[firstpage_image] =>[orig_patent_app_number] => 554749
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/554749 | Mesa semiconductor structure | Nov 6, 1995 | Issued |
Array
(
[id] => 3727574
[patent_doc_number] => 05682046
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-10-28
[patent_title] => 'Heterojunction bipolar semiconductor device and its manufacturing method'
[patent_app_type] => 1
[patent_app_number] => 8/553034
[patent_app_country] => US
[patent_app_date] => 1995-11-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 15
[patent_figures_cnt] => 30
[patent_no_of_words] => 10256
[patent_no_of_claims] => 36
[patent_no_of_ind_claims] => 8
[patent_words_short_claim] => 193
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/682/05682046.pdf
[firstpage_image] =>[orig_patent_app_number] => 553034
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/553034 | Heterojunction bipolar semiconductor device and its manufacturing method | Nov 2, 1995 | Issued |
Array
(
[id] => 3985243
[patent_doc_number] => 05949136
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-09-07
[patent_title] => 'High performance debug I/O'
[patent_app_type] => 1
[patent_app_number] => 8/551259
[patent_app_country] => US
[patent_app_date] => 1995-10-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 1916
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 147
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/949/05949136.pdf
[firstpage_image] =>[orig_patent_app_number] => 551259
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/551259 | High performance debug I/O | Oct 30, 1995 | Issued |
| 08/538855 | MOS LSI WITH PROTECTION STRUCTURE | Oct 3, 1995 | Abandoned |
Array
(
[id] => 3671903
[patent_doc_number] => 05600164
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-02-04
[patent_title] => 'Non-volatile semiconductor memory device'
[patent_app_type] => 1
[patent_app_number] => 8/536300
[patent_app_country] => US
[patent_app_date] => 1995-09-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 6
[patent_no_of_words] => 2815
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 109
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/600/05600164.pdf
[firstpage_image] =>[orig_patent_app_number] => 536300
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/536300 | Non-volatile semiconductor memory device | Sep 28, 1995 | Issued |
Array
(
[id] => 3865829
[patent_doc_number] => 05796149
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-08-18
[patent_title] => 'Semiconductor memory using different concentration impurity diffused layers'
[patent_app_type] => 1
[patent_app_number] => 8/524672
[patent_app_country] => US
[patent_app_date] => 1995-09-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 29
[patent_no_of_words] => 6257
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 107
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/796/05796149.pdf
[firstpage_image] =>[orig_patent_app_number] => 524672
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/524672 | Semiconductor memory using different concentration impurity diffused layers | Sep 7, 1995 | Issued |
Array
(
[id] => 3651535
[patent_doc_number] => 05637895
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-06-10
[patent_title] => 'Non-volatile semiconductor memory device'
[patent_app_type] => 1
[patent_app_number] => 8/523315
[patent_app_country] => US
[patent_app_date] => 1995-09-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 32
[patent_figures_cnt] => 54
[patent_no_of_words] => 10255
[patent_no_of_claims] => 33
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 147
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/637/05637895.pdf
[firstpage_image] =>[orig_patent_app_number] => 523315
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/523315 | Non-volatile semiconductor memory device | Sep 4, 1995 | Issued |
| 08/522832 | DYNAMIC RANDOM ACCESS MEMORY DEVICE COMPRISING MEMORY CELLS HAVING CAPACITOR FORMED ABOVE CELL TRANSISTOR AND PERIPHERAL CIRCUIT FOR IMPROVING SHAPE AND ASPECT RATIO OF CONTACT HOLE IN THE PERIPHERAL CIRCUIT AND PRODUCING METHOD THEREOF | Aug 31, 1995 | Abandoned |
Array
(
[id] => 3651442
[patent_doc_number] => 05637888
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-06-10
[patent_title] => 'Insulated gate thyristor'
[patent_app_type] => 1
[patent_app_number] => 8/521517
[patent_app_country] => US
[patent_app_date] => 1995-08-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 9
[patent_no_of_words] => 4260
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 192
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/637/05637888.pdf
[firstpage_image] =>[orig_patent_app_number] => 521517
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/521517 | Insulated gate thyristor | Aug 29, 1995 | Issued |
Array
(
[id] => 3652806
[patent_doc_number] => 05684319
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-11-04
[patent_title] => 'Self-aligned source and body contact structure for high performance DMOS transistors and method of fabricating same'
[patent_app_type] => 1
[patent_app_number] => 8/518785
[patent_app_country] => US
[patent_app_date] => 1995-08-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 22
[patent_no_of_words] => 5972
[patent_no_of_claims] => 43
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 228
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/684/05684319.pdf
[firstpage_image] =>[orig_patent_app_number] => 518785
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/518785 | Self-aligned source and body contact structure for high performance DMOS transistors and method of fabricating same | Aug 23, 1995 | Issued |
Array
(
[id] => 3663016
[patent_doc_number] => 05592009
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-01-07
[patent_title] => 'Semiconductor device having a floating node that can maintain a predetermined potential for long time, a semiconductor memory device having high data maintenance performance, and a method of manufacturing thereof'
[patent_app_type] => 1
[patent_app_number] => 8/516075
[patent_app_country] => US
[patent_app_date] => 1995-08-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 19
[patent_figures_cnt] => 28
[patent_no_of_words] => 9933
[patent_no_of_claims] => 30
[patent_no_of_ind_claims] => 13
[patent_words_short_claim] => 98
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/592/05592009.pdf
[firstpage_image] =>[orig_patent_app_number] => 516075
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/516075 | Semiconductor device having a floating node that can maintain a predetermined potential for long time, a semiconductor memory device having high data maintenance performance, and a method of manufacturing thereof | Aug 16, 1995 | Issued |
Array
(
[id] => 3844828
[patent_doc_number] => 05847417
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-12-08
[patent_title] => 'Semiconductor device and method of manufacturing same'
[patent_app_type] => 1
[patent_app_number] => 8/516405
[patent_app_country] => US
[patent_app_date] => 1995-08-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 30
[patent_no_of_words] => 8791
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 161
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/847/05847417.pdf
[firstpage_image] =>[orig_patent_app_number] => 516405
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/516405 | Semiconductor device and method of manufacturing same | Aug 16, 1995 | Issued |
Array
(
[id] => 3590376
[patent_doc_number] => 05552617
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-09-03
[patent_title] => 'Bipolar transistor'
[patent_app_type] => 1
[patent_app_number] => 8/515636
[patent_app_country] => US
[patent_app_date] => 1995-08-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 16
[patent_no_of_words] => 4170
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 63
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/552/05552617.pdf
[firstpage_image] =>[orig_patent_app_number] => 515636
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/515636 | Bipolar transistor | Aug 15, 1995 | Issued |
Array
(
[id] => 3548572
[patent_doc_number] => 05554870
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-09-10
[patent_title] => 'Integrated circuit having both vertical and horizontal devices and process for making the same'
[patent_app_type] => 1
[patent_app_number] => 8/510329
[patent_app_country] => US
[patent_app_date] => 1995-08-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 15
[patent_no_of_words] => 8004
[patent_no_of_claims] => 22
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 159
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/554/05554870.pdf
[firstpage_image] =>[orig_patent_app_number] => 510329
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/510329 | Integrated circuit having both vertical and horizontal devices and process for making the same | Aug 1, 1995 | Issued |
Array
(
[id] => 3698535
[patent_doc_number] => 05679971
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-10-21
[patent_title] => 'Semiconductor integrated circuit'
[patent_app_type] => 1
[patent_app_number] => 8/505459
[patent_app_country] => US
[patent_app_date] => 1995-07-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 18
[patent_no_of_words] => 7287
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 249
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/679/05679971.pdf
[firstpage_image] =>[orig_patent_app_number] => 505459
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/505459 | Semiconductor integrated circuit | Jul 20, 1995 | Issued |
Array
(
[id] => 3706922
[patent_doc_number] => 05675157
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-10-07
[patent_title] => 'Transferred electron effect device'
[patent_app_type] => 1
[patent_app_number] => 8/501893
[patent_app_country] => US
[patent_app_date] => 1995-07-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 10
[patent_no_of_words] => 6353
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 90
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/675/05675157.pdf
[firstpage_image] =>[orig_patent_app_number] => 501893
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/501893 | Transferred electron effect device | Jul 12, 1995 | Issued |
Array
(
[id] => 4091427
[patent_doc_number] => 06018172
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-01-25
[patent_title] => 'Semiconductor memory device including memory cell transistors formed on SOI substrate and having fixed body regions'
[patent_app_type] => 1
[patent_app_number] => 8/501525
[patent_app_country] => US
[patent_app_date] => 1995-07-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 59
[patent_figures_cnt] => 68
[patent_no_of_words] => 14908
[patent_no_of_claims] => 31
[patent_no_of_ind_claims] => 11
[patent_words_short_claim] => 108
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/018/06018172.pdf
[firstpage_image] =>[orig_patent_app_number] => 501525
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/501525 | Semiconductor memory device including memory cell transistors formed on SOI substrate and having fixed body regions | Jul 11, 1995 | Issued |
Array
(
[id] => 3882443
[patent_doc_number] => 05804842
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-09-08
[patent_title] => 'Optically writing erasable conductive patterns at a bandgap-engineered heterojunction'
[patent_app_type] => 1
[patent_app_number] => 8/493181
[patent_app_country] => US
[patent_app_date] => 1995-06-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 5
[patent_no_of_words] => 2337
[patent_no_of_claims] => 22
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 92
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/804/05804842.pdf
[firstpage_image] =>[orig_patent_app_number] => 493181
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/493181 | Optically writing erasable conductive patterns at a bandgap-engineered heterojunction | Jun 19, 1995 | Issued |
| 08/472295 | MICROCOMPUTER WITH HIGH DENSITY RAM {IN SEPARATE ISOLATIONWELL} ON SINGLE CHIP | Jun 6, 1995 | Abandoned |