Donald L. Monin Jr.

Array ( [id] => 3943329 [patent_doc_number] => 05872378 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-02-16 [patent_title] => 'Dual thin oxide ESD network for nonvolatile memory applications' [patent_app_type] => 1 [patent_app_number] => 8/834559 [patent_app_country] => US [patent_app_date] => 1997-04-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 14 [patent_no_of_words] => 3306 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 169 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/872/05872378.pdf [firstpage_image] =>[orig_patent_app_number] => 834559 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4210128 [patent_doc_number] => 06078090 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-06-20 [patent_title] => 'Trench-gated Schottky diode with integral clamping diode' [patent_app_type] => 1 [patent_app_number] => 8/832012 [patent_app_country] => US [patent_app_date] => 1997-04-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 51 [patent_figures_cnt] => 78 [patent_no_of_words] => 11157 [patent_no_of_claims] => 66 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/078/06078090.pdf [firstpage_image] =>[orig_patent_app_number] => 832012 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3812117 [patent_doc_number] => 05854504 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-12-29 [patent_title] => 'Process tolerant NMOS transistor for electrostatic discharge protection' [patent_app_type] => 1 [patent_app_number] => 8/832771 [patent_app_country] => US [patent_app_date] => 1997-04-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 3980 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/854/05854504.pdf [firstpage_image] =>[orig_patent_app_number] => 832771 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4179847 [patent_doc_number] => 06084279 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-07-04 [patent_title] => 'Semiconductor device having a metal containing layer overlying a gate dielectric' [patent_app_type] => 1 [patent_app_number] => 8/831287 [patent_app_country] => US [patent_app_date] => 1997-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 11 [patent_no_of_words] => 3627 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 48 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/084/06084279.pdf [firstpage_image] =>[orig_patent_app_number] => 831287 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3938783 [patent_doc_number] => 05939749 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-08-17 [patent_title] => 'Split gate transistor array' [patent_app_type] => 1 [patent_app_number] => 8/824213 [patent_app_country] => US [patent_app_date] => 1997-03-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 26 [patent_no_of_words] => 7446 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 180 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/939/05939749.pdf [firstpage_image] =>[orig_patent_app_number] => 824213 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4015960 [patent_doc_number] => 05923949 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-07-13 [patent_title] => 'Semiconductor device having fluorine bearing sidewall spacers and method of manufacture thereof' [patent_app_type] => 1 [patent_app_number] => 8/822223 [patent_app_country] => US [patent_app_date] => 1997-03-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 13 [patent_no_of_words] => 2772 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 50 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/923/05923949.pdf [firstpage_image] =>[orig_patent_app_number] => 822223 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3895978 [patent_doc_number] => 05834812 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-11-10 [patent_title] => 'Edge stripped BESOI wafer' [patent_app_type] => 1 [patent_app_number] => 8/820593 [patent_app_country] => US [patent_app_date] => 1997-03-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 13 [patent_no_of_words] => 2755 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/834/05834812.pdf [firstpage_image] =>[orig_patent_app_number] => 820593 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3884909 [patent_doc_number] => 05805013 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-09-08 [patent_title] => 'Non-volatile memory device having a floating gate with enhanced charge retention' [patent_app_type] => 1 [patent_app_number] => 8/815835 [patent_app_country] => US [patent_app_date] => 1997-03-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 12 [patent_no_of_words] => 6334 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/805/05805013.pdf [firstpage_image] =>[orig_patent_app_number] => 815835 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3864802 [patent_doc_number] => 05793087 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-08-11 [patent_title] => 'Segmented non-volatile memory array having multiple sources' [patent_app_type] => 1 [patent_app_number] => 8/814326 [patent_app_country] => US [patent_app_date] => 1997-03-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 15 [patent_no_of_words] => 12239 [patent_no_of_claims] => 35 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 159 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/793/05793087.pdf [firstpage_image] =>[orig_patent_app_number] => 814326 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4002895 [patent_doc_number] => 05923076 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-07-13 [patent_title] => 'Integrated device with pads' [patent_app_type] => 1 [patent_app_number] => 8/811577 [patent_app_country] => US [patent_app_date] => 1997-03-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 2490 [patent_no_of_claims] => 41 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/923/05923076.pdf [firstpage_image] =>[orig_patent_app_number] => 811577 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3938770 [patent_doc_number] => 05939748 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-08-17 [patent_title] => 'Storage capacitor having a refractory metal storage electrode and method of forming the same' [patent_app_type] => 1 [patent_app_number] => 8/803179 [patent_app_country] => US [patent_app_date] => 1997-02-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 10 [patent_no_of_words] => 12549 [patent_no_of_claims] => 50 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/939/05939748.pdf [firstpage_image] =>[orig_patent_app_number] => 803179 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4145171 [patent_doc_number] => 06060746 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-05-09 [patent_title] => 'Power transistor having vertical FETs and method for making same' [patent_app_type] => 1 [patent_app_number] => 8/798663 [patent_app_country] => US [patent_app_date] => 1997-02-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 3835 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 220 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/060/06060746.pdf [firstpage_image] =>[orig_patent_app_number] => 798663 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4030692 [patent_doc_number] => 05883416 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-03-16 [patent_title] => 'Gate-contact structure to prevent contact metal penetration through gate layer without affecting breakdown voltage' [patent_app_type] => 1 [patent_app_number] => 8/792226 [patent_app_country] => US [patent_app_date] => 1997-01-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 3704 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/883/05883416.pdf [firstpage_image] =>[orig_patent_app_number] => 792226 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4140363 [patent_doc_number] => 06015977 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-01-18 [patent_title] => 'Integrated circuit memory cell having a small active area and method of forming same' [patent_app_type] => 1 [patent_app_number] => 8/790011 [patent_app_country] => US [patent_app_date] => 1997-01-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 8 [patent_no_of_words] => 3890 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 56 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/015/06015977.pdf [firstpage_image] =>[orig_patent_app_number] => 790011 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3830916 [patent_doc_number] => 05783845 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-07-21 [patent_title] => 'Semiconductor device and its manufacture utilizing crystal orientation dependence of impurity concentration' [patent_app_type] => 1 [patent_app_number] => 8/789665 [patent_app_country] => US [patent_app_date] => 1997-01-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 21 [patent_no_of_words] => 10828 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/783/05783845.pdf [firstpage_image] =>[orig_patent_app_number] => 789665 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3845309 [patent_doc_number] => 05744834 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-04-28 [patent_title] => 'Flash memory cell with tunnel oxide layer protected from thermal cycling' [patent_app_type] => 1 [patent_app_number] => 8/789213 [patent_app_country] => US [patent_app_date] => 1997-01-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 10 [patent_no_of_words] => 3020 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 278 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/744/05744834.pdf [firstpage_image] =>[orig_patent_app_number] => 789213 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3998330 [patent_doc_number] => 05892263 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-04-06 [patent_title] => 'CMOS device connected to at least three power supplies for preventing latch-up' [patent_app_type] => 1 [patent_app_number] => 8/784789 [patent_app_country] => US [patent_app_date] => 1997-01-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 10 [patent_no_of_words] => 2898 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 204 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/892/05892263.pdf [firstpage_image] =>[orig_patent_app_number] => 784789 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3775706 [patent_doc_number] => 05773848 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-06-30 [patent_title] => 'Thin film transistor with light antireflection layer' [patent_app_type] => 1 [patent_app_number] => 8/775071 [patent_app_country] => US [patent_app_date] => 1996-12-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 15 [patent_no_of_words] => 3178 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/773/05773848.pdf [firstpage_image] =>[orig_patent_app_number] => 775071 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3799389 [patent_doc_number] => 05780896 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-07-14 [patent_title] => 'Semiconductor device having shallow impurity region without short-circuit between gate electrode and source and drain regions and process of fabrication thereof' [patent_app_type] => 1 [patent_app_number] => 8/769423 [patent_app_country] => US [patent_app_date] => 1996-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 3714 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 237 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/780/05780896.pdf [firstpage_image] =>[orig_patent_app_number] => 769423 [rel_patent_id] =>[rel_patent_doc_number] =>)