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Donnell Alan Long

Examiner (ID: 17144)

Most Active Art Unit
3754
Art Unit(s)
3754
Total Applications
1541
Issued Applications
1147
Pending Applications
109
Abandoned Applications
316

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 18387850 [patent_doc_number] => 11658648 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2023-05-23 [patent_title] => Variation tolerant linear phase-interpolator [patent_app_type] => utility [patent_app_number] => 17/589682 [patent_app_country] => US [patent_app_date] => 2022-01-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 6065 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17589682 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/589682
Variation tolerant linear phase-interpolator Jan 30, 2022 Issued
Array ( [id] => 18782767 [patent_doc_number] => 11824544 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-11-21 [patent_title] => Phase correction circuit, and clock buffer and semiconductor apparatus including the same [patent_app_type] => utility [patent_app_number] => 17/585241 [patent_app_country] => US [patent_app_date] => 2022-01-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 6617 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 54 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17585241 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/585241
Phase correction circuit, and clock buffer and semiconductor apparatus including the same Jan 25, 2022 Issued
Array ( [id] => 17781061 [patent_doc_number] => 20220247411 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-08-04 [patent_title] => CLOCK-GATING SYNCHRONIZATION CIRCUIT AND METHOD OF CLOCK-GATING SYNCHRONIZATION [patent_app_type] => utility [patent_app_number] => 17/582735 [patent_app_country] => US [patent_app_date] => 2022-01-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5146 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -7 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17582735 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/582735
Clock-gating synchronization circuit and method of clock-gating synchronization Jan 23, 2022 Issued
Array ( [id] => 17964540 [patent_doc_number] => 20220345121 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-10-27 [patent_title] => WAVE-GENERATION CIRCUIT AND OPERATION SYSTEM UTILIZING THE SAME [patent_app_type] => utility [patent_app_number] => 17/581199 [patent_app_country] => US [patent_app_date] => 2022-01-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5867 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17581199 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/581199
Wave-generation circuit and operation system utilizing the same Jan 20, 2022 Issued
Array ( [id] => 18563473 [patent_doc_number] => 11728729 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2023-08-15 [patent_title] => Method and apparatus for delivering power to semiconductors [patent_app_type] => utility [patent_app_number] => 17/578065 [patent_app_country] => US [patent_app_date] => 2022-01-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 30 [patent_figures_cnt] => 34 [patent_no_of_words] => 16765 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 197 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17578065 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/578065
Method and apparatus for delivering power to semiconductors Jan 17, 2022 Issued
Array ( [id] => 17583977 [patent_doc_number] => 20220140832 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-05-05 [patent_title] => CLOCK GENERATION CIRCUIT AND SEMICONDUCTOR APPARATUS USING THE CLOCK GENERATION CIRCUIT [patent_app_type] => utility [patent_app_number] => 17/575413 [patent_app_country] => US [patent_app_date] => 2022-01-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 28092 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17575413 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/575413
Clock generation circuit and semiconductor apparatus using the clock generation circuit Jan 12, 2022 Issued
Array ( [id] => 18546782 [patent_doc_number] => 11720131 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-08-08 [patent_title] => Power supply circuit, power supply device, and motor vehicle including the same [patent_app_type] => utility [patent_app_number] => 17/570885 [patent_app_country] => US [patent_app_date] => 2022-01-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 14 [patent_no_of_words] => 4878 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17570885 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/570885
Power supply circuit, power supply device, and motor vehicle including the same Jan 6, 2022 Issued
Array ( [id] => 18255664 [patent_doc_number] => 20230082703 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-03-16 [patent_title] => SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 17/569222 [patent_app_country] => US [patent_app_date] => 2022-01-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8444 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17569222 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/569222
Semiconductor device Jan 4, 2022 Issued
Array ( [id] => 19766434 [patent_doc_number] => 12224742 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-02-11 [patent_title] => Switch device [patent_app_type] => utility [patent_app_number] => 18/259653 [patent_app_country] => US [patent_app_date] => 2021-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 12 [patent_no_of_words] => 14006 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18259653 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/259653
Switch device Dec 22, 2021 Issued
Array ( [id] => 19655095 [patent_doc_number] => 12176905 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-12-24 [patent_title] => Pipeline clock driving circuit, computing chip, hashboard and computing device [patent_app_type] => utility [patent_app_number] => 17/795777 [patent_app_country] => US [patent_app_date] => 2021-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 7198 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 248 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17795777 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/795777
Pipeline clock driving circuit, computing chip, hashboard and computing device Dec 20, 2021 Issued
Array ( [id] => 18261897 [patent_doc_number] => 11609597 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-03-21 [patent_title] => Wireline transceiver with internal and external clock generation [patent_app_type] => utility [patent_app_number] => 17/643995 [patent_app_country] => US [patent_app_date] => 2021-12-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6253 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17643995 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/643995
Wireline transceiver with internal and external clock generation Dec 12, 2021 Issued
Array ( [id] => 18156804 [patent_doc_number] => 11569805 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-01-31 [patent_title] => Minimum intrinsic timing utilization auto alignment on multi-die system [patent_app_type] => utility [patent_app_number] => 17/548571 [patent_app_country] => US [patent_app_date] => 2021-12-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2993 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 208 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17548571 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/548571
Minimum intrinsic timing utilization auto alignment on multi-die system Dec 11, 2021 Issued
Array ( [id] => 18195550 [patent_doc_number] => 20230049069 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-02-16 [patent_title] => CIRCUIT AND METHOD FOR ELIMINATING SPURIOUS SIGNAL [patent_app_type] => utility [patent_app_number] => 17/457790 [patent_app_country] => US [patent_app_date] => 2021-12-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7016 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -7 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17457790 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/457790
Circuit and method for eliminating spurious signal Dec 5, 2021 Issued
Array ( [id] => 17486841 [patent_doc_number] => 20220094345 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-03-24 [patent_title] => VARIABLE DELAY CIRCUIT AND SEMICONDUCTOR INTEGRATED CIRCUIT [patent_app_type] => utility [patent_app_number] => 17/457457 [patent_app_country] => US [patent_app_date] => 2021-12-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11579 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 440 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17457457 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/457457
Variable delay circuit and semiconductor integrated circuit Dec 2, 2021 Issued
Array ( [id] => 18424727 [patent_doc_number] => 20230179192 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-06-08 [patent_title] => APPARATUSES AND METHODS FOR DELAY MEASUREMENT INITIALIZATION [patent_app_type] => utility [patent_app_number] => 17/540846 [patent_app_country] => US [patent_app_date] => 2021-12-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7810 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 17 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17540846 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/540846
Apparatuses and methods for delay measurement initialization Dec 1, 2021 Issued
Array ( [id] => 17501399 [patent_doc_number] => 11290117 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2022-03-29 [patent_title] => Low-frequency arithmetic multiplying PLL for HDL devices [patent_app_type] => utility [patent_app_number] => 17/457162 [patent_app_country] => US [patent_app_date] => 2021-12-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 15 [patent_no_of_words] => 4223 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 166 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17457162 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/457162
Low-frequency arithmetic multiplying PLL for HDL devices Nov 30, 2021 Issued
Array ( [id] => 17994221 [patent_doc_number] => 20220360258 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-11-10 [patent_title] => DUTY-CYCLE CORRECTOR PHASE SHIFT CIRCUIT [patent_app_type] => utility [patent_app_number] => 17/538291 [patent_app_country] => US [patent_app_date] => 2021-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14337 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17538291 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/538291
Duty-cycle corrector phase shift circuit Nov 29, 2021 Issued
Array ( [id] => 18400627 [patent_doc_number] => 11662763 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2023-05-30 [patent_title] => Technique for clock alignment supporting reset isolation [patent_app_type] => utility [patent_app_number] => 17/537150 [patent_app_country] => US [patent_app_date] => 2021-11-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 5065 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17537150 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/537150
Technique for clock alignment supporting reset isolation Nov 28, 2021 Issued
Array ( [id] => 18156727 [patent_doc_number] => 11569728 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2023-01-31 [patent_title] => Error detection for power converter [patent_app_type] => utility [patent_app_number] => 17/456848 [patent_app_country] => US [patent_app_date] => 2021-11-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 7118 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17456848 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/456848
Error detection for power converter Nov 28, 2021 Issued
Array ( [id] => 17631396 [patent_doc_number] => 20220166411 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-05-26 [patent_title] => TERMINATION IMPEDANCE ISOLATION FOR DIFFERENTIAL TRANSMISSION AND RELATED SYSTEMS, METHODS AND APPARATUSES [patent_app_type] => utility [patent_app_number] => 17/456432 [patent_app_country] => US [patent_app_date] => 2021-11-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7352 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 58 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17456432 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/456432
Termination impedance isolation for differential transmission and related systems, methods and apparatuses Nov 23, 2021 Issued
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