Search

Donnell Alan Long

Examiner (ID: 17144)

Most Active Art Unit
3754
Art Unit(s)
3754
Total Applications
1541
Issued Applications
1147
Pending Applications
109
Abandoned Applications
316

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 8604369 [patent_doc_number] => 20130009681 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-01-10 [patent_title] => 'ADPLL CIRCUIT, SEMICONDUCTOR DEVICE, AND PORTABLE INFORMATION DEVICE' [patent_app_type] => utility [patent_app_number] => 13/616449 [patent_app_country] => US [patent_app_date] => 2012-09-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 6283 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13616449 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/616449
ADPLL circuit, semiconductor device, and portable information device Sep 13, 2012 Issued
Array ( [id] => 8889131 [patent_doc_number] => 20130162315 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-06-27 [patent_title] => 'SIGNAL TRANSMISSION/RECEPTION SYSTEM' [patent_app_type] => utility [patent_app_number] => 13/619632 [patent_app_country] => US [patent_app_date] => 2012-09-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3638 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13619632 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/619632
Signal transmission/reception system Sep 13, 2012 Issued
Array ( [id] => 8743026 [patent_doc_number] => 20130082743 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-04-04 [patent_title] => 'SEMICONDUCTOR DEVICE GENERATES COMPLEMENTARY OUTPUT SIGNALS' [patent_app_type] => utility [patent_app_number] => 13/610541 [patent_app_country] => US [patent_app_date] => 2012-09-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 4707 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13610541 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/610541
Semiconductor device generates complementary output signals Sep 10, 2012 Issued
Array ( [id] => 8583502 [patent_doc_number] => 20130002324 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-01-03 [patent_title] => 'CIRCUITS AND METHODS FOR CLOCK SIGNAL DUTY-CYCLE CORRECTION' [patent_app_type] => utility [patent_app_number] => 13/610526 [patent_app_country] => US [patent_app_date] => 2012-09-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4119 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13610526 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/610526
Circuits and methods for clock signal duty-cycle correction Sep 10, 2012 Issued
Array ( [id] => 8518026 [patent_doc_number] => 20120317435 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-12-13 [patent_title] => 'APPARATUS FOR DETECTING PRESENCE OR ABSENCE OF OSCILLATION OF CLOCK SIGNAL' [patent_app_type] => utility [patent_app_number] => 13/591521 [patent_app_country] => US [patent_app_date] => 2012-08-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5007 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13591521 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/591521
Apparatus for detecting presence or absence of oscillation of clock signal Aug 21, 2012 Issued
Array ( [id] => 8509910 [patent_doc_number] => 20120309318 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-12-06 [patent_title] => 'WIRELESS COMMUNICATION SYSTEM, WIRELESS COMMUNICATION DEVICE, WIRELESS COMMUNICATION METHOD AND PROGRAM' [patent_app_type] => utility [patent_app_number] => 13/572244 [patent_app_country] => US [patent_app_date] => 2012-08-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 9934 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13572244 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/572244
Wireless communication system, wireless communication device, wireless communication method and program Aug 9, 2012 Issued
Array ( [id] => 9764519 [patent_doc_number] => 08848858 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-09-30 [patent_title] => 'Integrated non-volatile monotonic counters' [patent_app_type] => utility [patent_app_number] => 13/564497 [patent_app_country] => US [patent_app_date] => 2012-08-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 10603 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 13 [patent_words_short_claim] => 62 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13564497 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/564497
Integrated non-volatile monotonic counters Jul 31, 2012 Issued
Array ( [id] => 9609168 [patent_doc_number] => 08786342 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2014-07-22 [patent_title] => 'GaN HEMT power transistor pulse leveling circuit' [patent_app_type] => utility [patent_app_number] => 13/563155 [patent_app_country] => US [patent_app_date] => 2012-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3623 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13563155 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/563155
GaN HEMT power transistor pulse leveling circuit Jul 30, 2012 Issued
Array ( [id] => 9145950 [patent_doc_number] => 20130300473 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-11-14 [patent_title] => 'PHASE-LOCKED LOOP (PLL) FAIL-OVER CIRCUIT TECHNIQUE AND METHOD TO MITIGATE EFFECTS OF SINGLE-EVENT TRANSIENTS' [patent_app_type] => utility [patent_app_number] => 13/560774 [patent_app_country] => US [patent_app_date] => 2012-07-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 5514 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13560774 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/560774
Phase-locked loop (PLL) fail-over circuit technique and method to mitigate effects of single-event transients Jul 26, 2012 Issued
Array ( [id] => 8803037 [patent_doc_number] => 08441314 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2013-05-14 [patent_title] => 'Configurable clock network for programmable logic device' [patent_app_type] => utility [patent_app_number] => 13/558904 [patent_app_country] => US [patent_app_date] => 2012-07-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4708 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 50 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13558904 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/558904
Configurable clock network for programmable logic device Jul 25, 2012 Issued
Array ( [id] => 9390166 [patent_doc_number] => 08686776 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-04-01 [patent_title] => 'Phase rotator based on voltage referencing' [patent_app_type] => utility [patent_app_number] => 13/556237 [patent_app_country] => US [patent_app_date] => 2012-07-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 17 [patent_no_of_words] => 5555 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 58 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13556237 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/556237
Phase rotator based on voltage referencing Jul 23, 2012 Issued
Array ( [id] => 8592736 [patent_doc_number] => 08350613 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-01-08 [patent_title] => 'Signal delay circuit, clock transfer control circuit and semiconductor device having the same' [patent_app_type] => utility [patent_app_number] => 13/552037 [patent_app_country] => US [patent_app_date] => 2012-07-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 3381 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13552037 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/552037
Signal delay circuit, clock transfer control circuit and semiconductor device having the same Jul 17, 2012 Issued
Array ( [id] => 8803016 [patent_doc_number] => 08441293 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-05-14 [patent_title] => 'Method and apparatus for pulse width modulation' [patent_app_type] => utility [patent_app_number] => 13/548070 [patent_app_country] => US [patent_app_date] => 2012-07-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3320 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13548070 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/548070
Method and apparatus for pulse width modulation Jul 11, 2012 Issued
Array ( [id] => 9649550 [patent_doc_number] => 08803572 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-08-12 [patent_title] => 'Phase locked loop circuit with reduced jitter' [patent_app_type] => utility [patent_app_number] => 13/547742 [patent_app_country] => US [patent_app_date] => 2012-07-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 4529 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 50 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13547742 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/547742
Phase locked loop circuit with reduced jitter Jul 11, 2012 Issued
Array ( [id] => 8786405 [patent_doc_number] => 08433257 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-04-30 [patent_title] => 'Integrated waveguide transceiver' [patent_app_type] => utility [patent_app_number] => 13/539721 [patent_app_country] => US [patent_app_date] => 2012-07-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 5186 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 40 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13539721 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/539721
Integrated waveguide transceiver Jul 1, 2012 Issued
Array ( [id] => 9087166 [patent_doc_number] => 08558597 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-10-15 [patent_title] => 'High-resolution phase interpolators' [patent_app_type] => utility [patent_app_number] => 13/538621 [patent_app_country] => US [patent_app_date] => 2012-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 8629 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 239 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13538621 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/538621
High-resolution phase interpolators Jun 28, 2012 Issued
Array ( [id] => 9627388 [patent_doc_number] => 08797074 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-08-05 [patent_title] => 'Semiconductor device having DLL circuit and control method thereof' [patent_app_type] => utility [patent_app_number] => 13/538429 [patent_app_country] => US [patent_app_date] => 2012-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 8071 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13538429 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/538429
Semiconductor device having DLL circuit and control method thereof Jun 28, 2012 Issued
Array ( [id] => 9100469 [patent_doc_number] => 08564352 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-10-22 [patent_title] => 'High-resolution phase interpolators' [patent_app_type] => utility [patent_app_number] => 13/538276 [patent_app_country] => US [patent_app_date] => 2012-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 8614 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 248 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13538276 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/538276
High-resolution phase interpolators Jun 28, 2012 Issued
Array ( [id] => 9260319 [patent_doc_number] => 20130342248 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-12-26 [patent_title] => 'Low Power Oversampling With Delay Locked Loop Implementation' [patent_app_type] => utility [patent_app_number] => 13/531748 [patent_app_country] => US [patent_app_date] => 2012-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 6062 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13531748 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/531748
Low power oversampling with delay locked loop implementation Jun 24, 2012 Issued
Array ( [id] => 9274209 [patent_doc_number] => 08638145 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-01-28 [patent_title] => 'Method for locking a delay locked loop' [patent_app_type] => utility [patent_app_number] => 13/529671 [patent_app_country] => US [patent_app_date] => 2012-06-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5673 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 171 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13529671 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/529671
Method for locking a delay locked loop Jun 20, 2012 Issued
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