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Donnell Alan Long

Examiner (ID: 17144)

Most Active Art Unit
3754
Art Unit(s)
3754
Total Applications
1541
Issued Applications
1147
Pending Applications
109
Abandoned Applications
316

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 8937892 [patent_doc_number] => 20130187689 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-07-25 [patent_title] => 'PHASE-LOCKED LOOP WITH TWO NEGATIVE FEEDBACK LOOPS' [patent_app_type] => utility [patent_app_number] => 13/353477 [patent_app_country] => US [patent_app_date] => 2012-01-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4955 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13353477 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/353477
Phase-locked loop with two negative feedback loops Jan 18, 2012 Issued
Array ( [id] => 8181042 [patent_doc_number] => 20120112812 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-05-10 [patent_title] => 'CLOCK GENERATOR, PULSE GENERATOR UTILIZING THE CLOCK GENERATOR, AND METHODS THEREOF' [patent_app_type] => utility [patent_app_number] => 13/354315 [patent_app_country] => US [patent_app_date] => 2012-01-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 6089 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0112/20120112812.pdf [firstpage_image] =>[orig_patent_app_number] => 13354315 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/354315
Clock generator, pulse generator utilizing the clock generator, and methods thereof Jan 18, 2012 Issued
Array ( [id] => 8777862 [patent_doc_number] => 20130099837 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-04-25 [patent_title] => 'PHASE MIXER AND DELAY LOCKED LOOP INCLUDING THE SAME' [patent_app_type] => utility [patent_app_number] => 13/353716 [patent_app_country] => US [patent_app_date] => 2012-01-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 8561 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13353716 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/353716
Phase mixer and delay locked loop including the same Jan 18, 2012 Issued
Array ( [id] => 8340893 [patent_doc_number] => 08242825 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-08-14 [patent_title] => 'Method and apparatus for pulse width modulation' [patent_app_type] => utility [patent_app_number] => 13/350455 [patent_app_country] => US [patent_app_date] => 2012-01-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3287 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 172 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13350455 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/350455
Method and apparatus for pulse width modulation Jan 12, 2012 Issued
Array ( [id] => 8377401 [patent_doc_number] => 08260205 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-09-04 [patent_title] => 'Wireless communication system, wireless communication device, wireless communication method and program' [patent_app_type] => utility [patent_app_number] => 13/348305 [patent_app_country] => US [patent_app_date] => 2012-01-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 15 [patent_no_of_words] => 9916 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 170 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13348305 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/348305
Wireless communication system, wireless communication device, wireless communication method and program Jan 10, 2012 Issued
Array ( [id] => 10597940 [patent_doc_number] => 09319039 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-04-19 [patent_title] => 'Forwarded clock jitter reduction' [patent_app_type] => utility [patent_app_number] => 13/976877 [patent_app_country] => US [patent_app_date] => 2011-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 7 [patent_no_of_words] => 3038 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 57 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13976877 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/976877
Forwarded clock jitter reduction Dec 29, 2011 Issued
Array ( [id] => 8785360 [patent_doc_number] => 08432207 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2013-04-30 [patent_title] => 'Method and apparatus for correcting the duty cycle of a high speed clock' [patent_app_type] => utility [patent_app_number] => 13/341017 [patent_app_country] => US [patent_app_date] => 2011-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2514 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13341017 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/341017
Method and apparatus for correcting the duty cycle of a high speed clock Dec 29, 2011 Issued
Array ( [id] => 10107333 [patent_doc_number] => 09143120 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-09-22 [patent_title] => 'Mechanisms for clock gating' [patent_app_type] => utility [patent_app_number] => 13/997840 [patent_app_country] => US [patent_app_date] => 2011-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 4617 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13997840 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/997840
Mechanisms for clock gating Dec 21, 2011 Issued
Array ( [id] => 8140095 [patent_doc_number] => 20120094595 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-04-19 [patent_title] => 'COMMUNICATION APPARATUS AND COMMUNICATION SYSTEM' [patent_app_type] => utility [patent_app_number] => 13/333567 [patent_app_country] => US [patent_app_date] => 2011-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6407 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0094/20120094595.pdf [firstpage_image] =>[orig_patent_app_number] => 13333567 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/333567
Communication apparatus and communication system Dec 20, 2011 Issued
Array ( [id] => 8889126 [patent_doc_number] => 20130162310 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-06-27 [patent_title] => 'CLOCK GENERATOR WITH INTEGRATED PHASE OFFSET PROGRAMMABILITY' [patent_app_type] => utility [patent_app_number] => 13/333011 [patent_app_country] => US [patent_app_date] => 2011-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 6025 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13333011 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/333011
Clock generator with integrated phase offset programmability Dec 20, 2011 Issued
Array ( [id] => 9255420 [patent_doc_number] => 08618843 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-12-31 [patent_title] => 'High speed serial input/output bus voltage mode driver with tunable amplitude and resistance' [patent_app_type] => utility [patent_app_number] => 13/333095 [patent_app_country] => US [patent_app_date] => 2011-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2273 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13333095 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/333095
High speed serial input/output bus voltage mode driver with tunable amplitude and resistance Dec 20, 2011 Issued
Array ( [id] => 8583503 [patent_doc_number] => 20130002323 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-01-03 [patent_title] => 'DUTY CYCLE CORRECTION CIRCUIT' [patent_app_type] => utility [patent_app_number] => 13/332964 [patent_app_country] => US [patent_app_date] => 2011-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4476 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13332964 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/332964
Duty cycle correction circuit Dec 20, 2011 Issued
Array ( [id] => 8676341 [patent_doc_number] => 08384458 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2013-02-26 [patent_title] => 'Phase interpolation circuit' [patent_app_type] => utility [patent_app_number] => 13/330615 [patent_app_country] => US [patent_app_date] => 2011-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4612 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 238 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13330615 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/330615
Phase interpolation circuit Dec 18, 2011 Issued
Array ( [id] => 8610583 [patent_doc_number] => 20130015896 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-01-17 [patent_title] => 'PHASE-LOCKED LOOP APPARATUS AND TUNING VOLTAGE PROVIDING CIRCUIT THEREOF' [patent_app_type] => utility [patent_app_number] => 13/313020 [patent_app_country] => US [patent_app_date] => 2011-12-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3793 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13313020 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/313020
Phase-locked loop apparatus and tuning voltage providing circuit thereof Dec 6, 2011 Issued
Array ( [id] => 8225390 [patent_doc_number] => 20120139596 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-06-07 [patent_title] => 'CIRCUITRY FOR CLOCK AND METHOD FOR PROVIDING CLOCK SIGNAL' [patent_app_type] => utility [patent_app_number] => 13/311069 [patent_app_country] => US [patent_app_date] => 2011-12-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5917 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13311069 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/311069
Circuitry for clock and method for providing clock signal Dec 4, 2011 Issued
Array ( [id] => 9075200 [patent_doc_number] => 08552782 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2013-10-08 [patent_title] => 'Quadrature phase network' [patent_app_type] => utility [patent_app_number] => 13/307930 [patent_app_country] => US [patent_app_date] => 2011-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 4267 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 153 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13307930 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/307930
Quadrature phase network Nov 29, 2011 Issued
Array ( [id] => 7819937 [patent_doc_number] => 20120066557 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-03-15 [patent_title] => 'APPARATUS FOR DETECTING PRESENCE OR ABSENCE OF OSCILLATION OF CLOCK SIGNAL' [patent_app_type] => utility [patent_app_number] => 13/303697 [patent_app_country] => US [patent_app_date] => 2011-11-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4980 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0066/20120066557.pdf [firstpage_image] =>[orig_patent_app_number] => 13303697 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/303697
Apparatus for detecting presence or absence of oscillation of clock signal Nov 22, 2011 Issued
Array ( [id] => 9051716 [patent_doc_number] => 20130249430 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-09-26 [patent_title] => 'ADAPTABLE DRIVER CIRCUIT FOR DRIVING A LIGHT CIRCUIT' [patent_app_type] => utility [patent_app_number] => 13/989472 [patent_app_country] => US [patent_app_date] => 2011-11-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 4383 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13989472 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/989472
Adaptable driver circuit for driving a light circuit Nov 21, 2011 Issued
Array ( [id] => 8340886 [patent_doc_number] => 08242820 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-08-14 [patent_title] => 'Phase locked loop and method for operating the same' [patent_app_type] => utility [patent_app_number] => 13/301117 [patent_app_country] => US [patent_app_date] => 2011-11-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 4301 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 59 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13301117 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/301117
Phase locked loop and method for operating the same Nov 20, 2011 Issued
Array ( [id] => 8933412 [patent_doc_number] => 08493117 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-07-23 [patent_title] => 'Leakage tolerant delay locked loop circuit device' [patent_app_type] => utility [patent_app_number] => 13/295351 [patent_app_country] => US [patent_app_date] => 2011-11-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6855 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 215 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13295351 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/295351
Leakage tolerant delay locked loop circuit device Nov 13, 2011 Issued
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