Search

Donnell Alan Long

Examiner (ID: 17144)

Most Active Art Unit
3754
Art Unit(s)
3754
Total Applications
1541
Issued Applications
1147
Pending Applications
109
Abandoned Applications
316

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 8847023 [patent_doc_number] => 08456210 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-06-04 [patent_title] => 'Delay locked loop with offset correction' [patent_app_type] => utility [patent_app_number] => 12/961523 [patent_app_country] => US [patent_app_date] => 2010-12-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 12 [patent_no_of_words] => 7898 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12961523 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/961523
Delay locked loop with offset correction Dec 6, 2010 Issued
Array ( [id] => 8318043 [patent_doc_number] => 08232821 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-07-31 [patent_title] => 'Clock data recovery circuit' [patent_app_type] => utility [patent_app_number] => 12/957523 [patent_app_country] => US [patent_app_date] => 2010-12-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 12 [patent_no_of_words] => 6871 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 353 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12957523 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/957523
Clock data recovery circuit Nov 30, 2010 Issued
Array ( [id] => 6138523 [patent_doc_number] => 20110128058 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-06-02 [patent_title] => 'SIGNAL PROCESSING DEVICE' [patent_app_type] => utility [patent_app_number] => 12/957079 [patent_app_country] => US [patent_app_date] => 2010-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 10814 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0128/20110128058.pdf [firstpage_image] =>[orig_patent_app_number] => 12957079 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/957079
Signal processing device Nov 29, 2010 Issued
Array ( [id] => 6076220 [patent_doc_number] => 20110140747 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-06-16 [patent_title] => 'ADPLL CIRCUIT, SEMICONDUCTOR DEVICE, AND PORTABLE INFORMATION DEVICE' [patent_app_type] => utility [patent_app_number] => 12/955192 [patent_app_country] => US [patent_app_date] => 2010-11-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 6242 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0140/20110140747.pdf [firstpage_image] =>[orig_patent_app_number] => 12955192 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/955192
ADPLL circuit, semiconductor device, and portable information device Nov 28, 2010 Issued
Array ( [id] => 7979025 [patent_doc_number] => 08072260 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2011-12-06 [patent_title] => 'Configurable clock network for programmable logic device' [patent_app_type] => utility [patent_app_number] => 12/951486 [patent_app_country] => US [patent_app_date] => 2010-11-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4647 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/072/08072260.pdf [firstpage_image] =>[orig_patent_app_number] => 12951486 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/951486
Configurable clock network for programmable logic device Nov 21, 2010 Issued
Array ( [id] => 8352776 [patent_doc_number] => 08248106 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2012-08-21 [patent_title] => 'Lock detection using a digital phase error message' [patent_app_type] => utility [patent_app_number] => 12/949427 [patent_app_country] => US [patent_app_date] => 2010-11-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 13 [patent_no_of_words] => 6362 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12949427 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/949427
Lock detection using a digital phase error message Nov 17, 2010 Issued
Array ( [id] => 6004759 [patent_doc_number] => 20110057699 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-03-10 [patent_title] => 'INTEGRATED CIRCUIT AND PROGRAMMABLE DELAY' [patent_app_type] => utility [patent_app_number] => 12/939468 [patent_app_country] => US [patent_app_date] => 2010-11-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 7650 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0057/20110057699.pdf [firstpage_image] =>[orig_patent_app_number] => 12939468 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/939468
Integrated circuit and programmable delay Nov 3, 2010 Issued
Array ( [id] => 9141180 [patent_doc_number] => 08581649 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-11-12 [patent_title] => 'Semiconductor device and information processing system' [patent_app_type] => utility [patent_app_number] => 12/926255 [patent_app_country] => US [patent_app_date] => 2010-11-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 38 [patent_figures_cnt] => 41 [patent_no_of_words] => 14952 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 274 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12926255 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/926255
Semiconductor device and information processing system Nov 3, 2010 Issued
Array ( [id] => 8921734 [patent_doc_number] => 08487676 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-07-16 [patent_title] => 'Device for generating clock signals for asymmetric comparison of phase errors' [patent_app_type] => utility [patent_app_number] => 13/503738 [patent_app_country] => US [patent_app_date] => 2010-10-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 14 [patent_no_of_words] => 7600 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 330 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13503738 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/503738
Device for generating clock signals for asymmetric comparison of phase errors Oct 27, 2010 Issued
Array ( [id] => 5926960 [patent_doc_number] => 20110037752 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-02-17 [patent_title] => 'CIRCUIT FOR DISCHARGING AN ELECTRICAL LOAD, POWER OUTPUT STAGE COMPRISING SUCH A DISCHARGE CIRCUIT FOR THE CONTROL OF PLASMA DISPLAY CELLS; AND RELATED SYSTEM AND METHOD' [patent_app_type] => utility [patent_app_number] => 12/913613 [patent_app_country] => US [patent_app_date] => 2010-10-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5411 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0037/20110037752.pdf [firstpage_image] =>[orig_patent_app_number] => 12913613 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/913613
Circuit for discharging an electrical load, power output stage comprising such a discharge circuit for the control of plasma display cells; and related system and method Oct 26, 2010 Issued
Array ( [id] => 9750467 [patent_doc_number] => 08841950 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-09-23 [patent_title] => 'Pulse width modulation for switching amplifier' [patent_app_type] => utility [patent_app_number] => 13/500575 [patent_app_country] => US [patent_app_date] => 2010-10-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 8504 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13500575 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/500575
Pulse width modulation for switching amplifier Oct 7, 2010 Issued
Array ( [id] => 8123877 [patent_doc_number] => 20120086489 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-04-12 [patent_title] => 'ADAPTIVE QUADRATURE CORRECTION FOR QUADRATURE CLOCK PATH DESKEW' [patent_app_type] => utility [patent_app_number] => 12/901313 [patent_app_country] => US [patent_app_date] => 2010-10-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4778 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0086/20120086489.pdf [firstpage_image] =>[orig_patent_app_number] => 12901313 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/901313
Adaptive quadrature correction for quadrature clock path deskew Oct 7, 2010 Issued
Array ( [id] => 7753072 [patent_doc_number] => 08111093 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-02-07 [patent_title] => 'Power supply noise rejection in PLL or DLL circuits' [patent_app_type] => utility [patent_app_number] => 12/900949 [patent_app_country] => US [patent_app_date] => 2010-10-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 6695 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/111/08111093.pdf [firstpage_image] =>[orig_patent_app_number] => 12900949 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/900949
Power supply noise rejection in PLL or DLL circuits Oct 7, 2010 Issued
Array ( [id] => 9274212 [patent_doc_number] => 08638148 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-01-28 [patent_title] => 'Edge rate control' [patent_app_type] => utility [patent_app_number] => 12/899810 [patent_app_country] => US [patent_app_date] => 2010-10-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5960 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 192 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12899810 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/899810
Edge rate control Oct 6, 2010 Issued
Array ( [id] => 5990334 [patent_doc_number] => 20110012656 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-01-20 [patent_title] => 'SEMICONDUCTOR INTEGRATED CIRCUIT' [patent_app_type] => utility [patent_app_number] => 12/890253 [patent_app_country] => US [patent_app_date] => 2010-09-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 28 [patent_no_of_words] => 12203 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0012/20110012656.pdf [firstpage_image] =>[orig_patent_app_number] => 12890253 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/890253
Semiconductor integrated circuit Sep 23, 2010 Issued
Array ( [id] => 8550062 [patent_doc_number] => 08324948 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2012-12-04 [patent_title] => 'Method and apparatus for duty-cycle correction with reduced current consumption' [patent_app_type] => utility [patent_app_number] => 12/889254 [patent_app_country] => US [patent_app_date] => 2010-09-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 3722 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 46 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12889254 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/889254
Method and apparatus for duty-cycle correction with reduced current consumption Sep 22, 2010 Issued
Array ( [id] => 6131724 [patent_doc_number] => 20110006821 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-01-13 [patent_title] => 'System and Method for Signal Adjustment' [patent_app_type] => utility [patent_app_number] => 12/886791 [patent_app_country] => US [patent_app_date] => 2010-09-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4482 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0006/20110006821.pdf [firstpage_image] =>[orig_patent_app_number] => 12886791 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/886791
System and method for signal adjustment Sep 20, 2010 Issued
Array ( [id] => 6131720 [patent_doc_number] => 20110006819 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-01-13 [patent_title] => 'LEVEL-RESTORED SUPPLY-REGULATED PLL' [patent_app_type] => utility [patent_app_number] => 12/887174 [patent_app_country] => US [patent_app_date] => 2010-09-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6824 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0006/20110006819.pdf [firstpage_image] =>[orig_patent_app_number] => 12887174 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/887174
Level-restorer for supply-regulated PLL Sep 20, 2010 Issued
Array ( [id] => 8514269 [patent_doc_number] => 20120313677 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-12-13 [patent_title] => 'PHASE LOCKED LOOP' [patent_app_type] => utility [patent_app_number] => 13/510578 [patent_app_country] => US [patent_app_date] => 2010-09-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5419 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13510578 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/510578
Phase locked loop Sep 16, 2010 Issued
Array ( [id] => 7751490 [patent_doc_number] => 20120025927 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-02-02 [patent_title] => 'RF ISOLATION SWITCH CIRCUIT' [patent_app_type] => utility [patent_app_number] => 12/883940 [patent_app_country] => US [patent_app_date] => 2010-09-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 10216 [patent_no_of_claims] => 37 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0025/20120025927.pdf [firstpage_image] =>[orig_patent_app_number] => 12883940 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/883940
RF isolation switch circuit Sep 15, 2010 Issued
Menu