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Donnell Alan Long

Examiner (ID: 17144)

Most Active Art Unit
3754
Art Unit(s)
3754
Total Applications
1541
Issued Applications
1147
Pending Applications
109
Abandoned Applications
316

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 8083417 [patent_doc_number] => 08149030 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-04-03 [patent_title] => 'Clock generator to reduce long term jitter' [patent_app_type] => utility [patent_app_number] => 12/691023 [patent_app_country] => US [patent_app_date] => 2010-01-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4599 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/149/08149030.pdf [firstpage_image] =>[orig_patent_app_number] => 12691023 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/691023
Clock generator to reduce long term jitter Jan 20, 2010 Issued
Array ( [id] => 6488400 [patent_doc_number] => 20100259306 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-10-14 [patent_title] => 'PHASE LOCKED LOOP AND METHOD FOR CHARGING PHASE LOCKED LOOP' [patent_app_type] => utility [patent_app_number] => 12/690466 [patent_app_country] => US [patent_app_date] => 2010-01-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4990 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0259/20100259306.pdf [firstpage_image] =>[orig_patent_app_number] => 12690466 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/690466
Phase locked loop and method for charging phase locked loop Jan 19, 2010 Issued
Array ( [id] => 9184706 [patent_doc_number] => 08624647 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-01-07 [patent_title] => 'Duty cycle correction circuit for memory interfaces in integrated circuits' [patent_app_type] => utility [patent_app_number] => 12/690064 [patent_app_country] => US [patent_app_date] => 2010-01-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 11 [patent_no_of_words] => 6524 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12690064 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/690064
Duty cycle correction circuit for memory interfaces in integrated circuits Jan 18, 2010 Issued
Array ( [id] => 8318045 [patent_doc_number] => 08232824 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-07-31 [patent_title] => 'Clock circuit and method for pulsed latch circuits' [patent_app_type] => utility [patent_app_number] => 12/688741 [patent_app_country] => US [patent_app_date] => 2010-01-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 4514 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12688741 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/688741
Clock circuit and method for pulsed latch circuits Jan 14, 2010 Issued
Array ( [id] => 7551345 [patent_doc_number] => 08063680 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-11-22 [patent_title] => 'Delay locked loop circuit and semiconductor memory device including the same' [patent_app_type] => utility [patent_app_number] => 12/686633 [patent_app_country] => US [patent_app_date] => 2010-01-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 4295 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/063/08063680.pdf [firstpage_image] =>[orig_patent_app_number] => 12686633 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/686633
Delay locked loop circuit and semiconductor memory device including the same Jan 12, 2010 Issued
Array ( [id] => 5981285 [patent_doc_number] => 20110095808 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-04-28 [patent_title] => 'System and Method for Controlling Powered Device With Detachable, Controllable Switching Device' [patent_app_type] => utility [patent_app_number] => 12/684517 [patent_app_country] => US [patent_app_date] => 2010-01-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 7861 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0095/20110095808.pdf [firstpage_image] =>[orig_patent_app_number] => 12684517 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/684517
System and Method for Controlling Powered Device With Detachable, Controllable Switching Device Jan 7, 2010 Abandoned
Array ( [id] => 6099750 [patent_doc_number] => 20110163799 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-07-07 [patent_title] => 'Bi-directional Trimming Methods and Circuits for a Precise Band-Gap Reference' [patent_app_type] => utility [patent_app_number] => 12/651993 [patent_app_country] => US [patent_app_date] => 2010-01-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 5413 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0163/20110163799.pdf [firstpage_image] =>[orig_patent_app_number] => 12651993 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/651993
Bi-directional trimming methods and circuits for a precise band-gap reference Jan 3, 2010 Issued
Array ( [id] => 8447009 [patent_doc_number] => 08289066 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-10-16 [patent_title] => 'Gate control circuit for high bandwidth switch design' [patent_app_type] => utility [patent_app_number] => 12/650377 [patent_app_country] => US [patent_app_date] => 2009-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 16 [patent_no_of_words] => 5658 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12650377 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/650377
Gate control circuit for high bandwidth switch design Dec 29, 2009 Issued
Array ( [id] => 6437080 [patent_doc_number] => 20100188134 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-07-29 [patent_title] => 'CONTROL OF A RESONANT SWITCHING SYSTEM WITH MONITORING OF THE WORKING CURRENT IN AN OBSERVATION WINDOW' [patent_app_type] => utility [patent_app_number] => 12/649081 [patent_app_country] => US [patent_app_date] => 2009-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 10307 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0188/20100188134.pdf [firstpage_image] =>[orig_patent_app_number] => 12649081 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/649081
CONTROL OF A RESONANT SWITCHING SYSTEM WITH MONITORING OF THE WORKING CURRENT IN AN OBSERVATION WINDOW Dec 28, 2009 Abandoned
Array ( [id] => 8534131 [patent_doc_number] => 08310289 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-11-13 [patent_title] => 'Semiconductor apparatus' [patent_app_type] => utility [patent_app_number] => 12/648907 [patent_app_country] => US [patent_app_date] => 2009-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2413 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12648907 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/648907
Semiconductor apparatus Dec 28, 2009 Issued
Array ( [id] => 4528463 [patent_doc_number] => 07952403 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-05-31 [patent_title] => 'Update control apparatus in DLL circuit' [patent_app_type] => utility [patent_app_number] => 12/648516 [patent_app_country] => US [patent_app_date] => 2009-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4880 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/952/07952403.pdf [firstpage_image] =>[orig_patent_app_number] => 12648516 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/648516
Update control apparatus in DLL circuit Dec 28, 2009 Issued
Array ( [id] => 7551342 [patent_doc_number] => 08063677 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-11-22 [patent_title] => 'Phase locked loop and method for operating the same' [patent_app_type] => utility [patent_app_number] => 12/648816 [patent_app_country] => US [patent_app_date] => 2009-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 4269 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/063/08063677.pdf [firstpage_image] =>[orig_patent_app_number] => 12648816 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/648816
Phase locked loop and method for operating the same Dec 28, 2009 Issued
Array ( [id] => 8876645 [patent_doc_number] => 08471613 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-06-25 [patent_title] => 'Internal clock signal generator and operating method thereof' [patent_app_type] => utility [patent_app_number] => 12/648674 [patent_app_country] => US [patent_app_date] => 2009-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 4339 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12648674 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/648674
Internal clock signal generator and operating method thereof Dec 28, 2009 Issued
Array ( [id] => 6488382 [patent_doc_number] => 20100259305 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-10-14 [patent_title] => 'INJECTION LOCKED PHASE LOCK LOOPS' [patent_app_type] => utility [patent_app_number] => 12/648175 [patent_app_country] => US [patent_app_date] => 2009-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5152 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0259/20100259305.pdf [firstpage_image] =>[orig_patent_app_number] => 12648175 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/648175
INJECTION LOCKED PHASE LOCK LOOPS Dec 27, 2009 Abandoned
Array ( [id] => 7776151 [patent_doc_number] => 08120407 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2012-02-21 [patent_title] => 'Techniques for varying phase shifts in periodic signals' [patent_app_type] => utility [patent_app_number] => 12/642738 [patent_app_country] => US [patent_app_date] => 2009-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 10 [patent_no_of_words] => 6028 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/120/08120407.pdf [firstpage_image] =>[orig_patent_app_number] => 12642738 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/642738
Techniques for varying phase shifts in periodic signals Dec 17, 2009 Issued
Array ( [id] => 7998353 [patent_doc_number] => 08081024 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2011-12-20 [patent_title] => 'CMOS phase interpolation system' [patent_app_type] => utility [patent_app_number] => 12/640461 [patent_app_country] => US [patent_app_date] => 2009-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6217 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/081/08081024.pdf [firstpage_image] =>[orig_patent_app_number] => 12640461 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/640461
CMOS phase interpolation system Dec 16, 2009 Issued
Array ( [id] => 6282436 [patent_doc_number] => 20100156483 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-06-24 [patent_title] => 'DELAY LOCKED LOOP CIRCUIT' [patent_app_type] => utility [patent_app_number] => 12/638309 [patent_app_country] => US [patent_app_date] => 2009-12-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 7675 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0156/20100156483.pdf [firstpage_image] =>[orig_patent_app_number] => 12638309 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/638309
Delay locked loop circuit Dec 14, 2009 Issued
Array ( [id] => 6068425 [patent_doc_number] => 20110043274 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-02-24 [patent_title] => 'Apparatus and Methods for Registering Inputs from a User' [patent_app_type] => utility [patent_app_number] => 12/634377 [patent_app_country] => US [patent_app_date] => 2009-12-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4956 [patent_no_of_claims] => 44 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0043/20110043274.pdf [firstpage_image] =>[orig_patent_app_number] => 12634377 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/634377
Apparatus and methods for registering inputs from a user Dec 8, 2009 Issued
Array ( [id] => 6355434 [patent_doc_number] => 20100073053 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-03-25 [patent_title] => 'DELAY LOCKED LOOP FOR HIGH SPEED SEMICONDUCTOR MEMORY DEVICE' [patent_app_type] => utility [patent_app_number] => 12/631611 [patent_app_country] => US [patent_app_date] => 2009-12-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 4383 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0073/20100073053.pdf [firstpage_image] =>[orig_patent_app_number] => 12631611 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/631611
Delay locked loop for high speed semiconductor memory device Dec 3, 2009 Issued
Array ( [id] => 7989331 [patent_doc_number] => 08076964 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-12-13 [patent_title] => 'Sampling circuit' [patent_app_type] => utility [patent_app_number] => 12/630021 [patent_app_country] => US [patent_app_date] => 2009-12-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5068 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/076/08076964.pdf [firstpage_image] =>[orig_patent_app_number] => 12630021 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/630021
Sampling circuit Dec 2, 2009 Issued
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