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Donnell Alan Long

Examiner (ID: 17144)

Most Active Art Unit
3754
Art Unit(s)
3754
Total Applications
1541
Issued Applications
1147
Pending Applications
109
Abandoned Applications
316

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 6355464 [patent_doc_number] => 20100073059 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-03-25 [patent_title] => 'Duty control circuit and semiconductor device having the same' [patent_app_type] => utility [patent_app_number] => 12/585680 [patent_app_country] => US [patent_app_date] => 2009-09-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 9335 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0073/20100073059.pdf [firstpage_image] =>[orig_patent_app_number] => 12585680 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/585680
Duty control circuit and semiconductor device having the same Sep 21, 2009 Issued
Array ( [id] => 6564961 [patent_doc_number] => 20100017641 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-01-21 [patent_title] => 'Communication system communication device and method for determining duty ratio of PWM control' [patent_app_type] => utility [patent_app_number] => 12/585673 [patent_app_country] => US [patent_app_date] => 2009-09-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 7857 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0017/20100017641.pdf [firstpage_image] =>[orig_patent_app_number] => 12585673 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/585673
Communication system communication device and method for determining duty ratio of PWM control Sep 21, 2009 Issued
Array ( [id] => 6331018 [patent_doc_number] => 20100327929 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-12-30 [patent_title] => 'PREDETERMINED DUTY CYCLE SIGNAL GENERATOR' [patent_app_type] => utility [patent_app_number] => 12/558278 [patent_app_country] => US [patent_app_date] => 2009-09-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5401 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0327/20100327929.pdf [firstpage_image] =>[orig_patent_app_number] => 12558278 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/558278
Predetermined duty cycle signal generator Sep 10, 2009 Issued
Array ( [id] => 4619868 [patent_doc_number] => 07999589 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-08-16 [patent_title] => 'Circuits and methods for clock signal duty-cycle correction' [patent_app_type] => utility [patent_app_number] => 12/553792 [patent_app_country] => US [patent_app_date] => 2009-09-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 4053 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/999/07999589.pdf [firstpage_image] =>[orig_patent_app_number] => 12553792 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/553792
Circuits and methods for clock signal duty-cycle correction Sep 2, 2009 Issued
Array ( [id] => 4619867 [patent_doc_number] => 07999588 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2011-08-16 [patent_title] => 'Duty cycle correction circuitry' [patent_app_type] => utility [patent_app_number] => 12/551434 [patent_app_country] => US [patent_app_date] => 2009-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 4211 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/999/07999588.pdf [firstpage_image] =>[orig_patent_app_number] => 12551434 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/551434
Duty cycle correction circuitry Aug 30, 2009 Issued
Array ( [id] => 4458135 [patent_doc_number] => 07893747 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-02-22 [patent_title] => 'Control signal generation circuit' [patent_app_type] => utility [patent_app_number] => 12/583959 [patent_app_country] => US [patent_app_date] => 2009-08-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 2294 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/893/07893747.pdf [firstpage_image] =>[orig_patent_app_number] => 12583959 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/583959
Control signal generation circuit Aug 27, 2009 Issued
Array ( [id] => 5365360 [patent_doc_number] => 20090302919 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-12-10 [patent_title] => 'Phase Shifter' [patent_app_type] => utility [patent_app_number] => 12/542459 [patent_app_country] => US [patent_app_date] => 2009-08-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 3903 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0302/20090302919.pdf [firstpage_image] =>[orig_patent_app_number] => 12542459 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/542459
Phase shifter Aug 16, 2009 Issued
Array ( [id] => 7531017 [patent_doc_number] => 07843242 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2010-11-30 [patent_title] => 'Phase-shifted pulse width modulation signal generation' [patent_app_type] => utility [patent_app_number] => 12/537692 [patent_app_country] => US [patent_app_date] => 2009-08-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 10310 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 217 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/843/07843242.pdf [firstpage_image] =>[orig_patent_app_number] => 12537692 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/537692
Phase-shifted pulse width modulation signal generation Aug 6, 2009 Issued
Array ( [id] => 4610899 [patent_doc_number] => 07994837 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2011-08-09 [patent_title] => 'Techniques for phase interpolation' [patent_app_type] => utility [patent_app_number] => 12/537634 [patent_app_country] => US [patent_app_date] => 2009-08-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 7460 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/994/07994837.pdf [firstpage_image] =>[orig_patent_app_number] => 12537634 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/537634
Techniques for phase interpolation Aug 6, 2009 Issued
Array ( [id] => 4554958 [patent_doc_number] => 07961039 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-06-14 [patent_title] => 'Forwarded clock filtering' [patent_app_type] => utility [patent_app_number] => 12/536224 [patent_app_country] => US [patent_app_date] => 2009-08-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3861 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/961/07961039.pdf [firstpage_image] =>[orig_patent_app_number] => 12536224 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/536224
Forwarded clock filtering Aug 4, 2009 Issued
Array ( [id] => 4539917 [patent_doc_number] => 07888990 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2011-02-15 [patent_title] => 'Phase locked loop charge pump reference current bootstrapping' [patent_app_type] => utility [patent_app_number] => 12/498123 [patent_app_country] => US [patent_app_date] => 2009-07-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 13 [patent_no_of_words] => 7296 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/888/07888990.pdf [firstpage_image] =>[orig_patent_app_number] => 12498123 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/498123
Phase locked loop charge pump reference current bootstrapping Jul 5, 2009 Issued
Array ( [id] => 4512043 [patent_doc_number] => 07915941 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2011-03-29 [patent_title] => 'Phase interpolator circuits and methods' [patent_app_type] => utility [patent_app_number] => 12/496387 [patent_app_country] => US [patent_app_date] => 2009-07-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6654 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/915/07915941.pdf [firstpage_image] =>[orig_patent_app_number] => 12496387 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/496387
Phase interpolator circuits and methods Jun 30, 2009 Issued
Array ( [id] => 7764137 [patent_doc_number] => 08115534 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-02-14 [patent_title] => 'Analog switch controller' [patent_app_type] => utility [patent_app_number] => 12/494783 [patent_app_country] => US [patent_app_date] => 2009-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3600 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 47 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/115/08115534.pdf [firstpage_image] =>[orig_patent_app_number] => 12494783 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/494783
Analog switch controller Jun 29, 2009 Issued
Array ( [id] => 5493846 [patent_doc_number] => 20090261874 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-10-22 [patent_title] => 'Phase locked loop with small size and improved performance' [patent_app_type] => utility [patent_app_number] => 12/493700 [patent_app_country] => US [patent_app_date] => 2009-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 4929 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0261/20090261874.pdf [firstpage_image] =>[orig_patent_app_number] => 12493700 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/493700
Phase locked loop with small size and improved performance Jun 28, 2009 Issued
Array ( [id] => 6331010 [patent_doc_number] => 20100327928 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-12-30 [patent_title] => 'METHOD AND APPARATUS TO IMPROVE AND CONTROL THE PROPAGATION DELAY IN A CURRENT SLEWING CIRCUIT' [patent_app_type] => utility [patent_app_number] => 12/492252 [patent_app_country] => US [patent_app_date] => 2009-06-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2403 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0327/20100327928.pdf [firstpage_image] =>[orig_patent_app_number] => 12492252 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/492252
Method and apparatus to improve and control the propagation delay in a current slewing circuit Jun 25, 2009 Issued
Array ( [id] => 4528516 [patent_doc_number] => 07952408 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-05-31 [patent_title] => 'Embedded phase noise measurement system' [patent_app_type] => utility [patent_app_number] => 12/492893 [patent_app_country] => US [patent_app_date] => 2009-06-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 45 [patent_no_of_words] => 16114 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/952/07952408.pdf [firstpage_image] =>[orig_patent_app_number] => 12492893 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/492893
Embedded phase noise measurement system Jun 25, 2009 Issued
Array ( [id] => 9497506 [patent_doc_number] => 08736327 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-05-27 [patent_title] => 'Time-to-digital converter' [patent_app_type] => utility [patent_app_number] => 13/380392 [patent_app_country] => US [patent_app_date] => 2009-06-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 11 [patent_no_of_words] => 19528 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 367 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13380392 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/380392
Time-to-digital converter Jun 23, 2009 Issued
Array ( [id] => 4605196 [patent_doc_number] => 07986179 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-07-26 [patent_title] => 'Circuit and method for reducing popping sound' [patent_app_type] => utility [patent_app_number] => 12/483490 [patent_app_country] => US [patent_app_date] => 2009-06-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 2276 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/986/07986179.pdf [firstpage_image] =>[orig_patent_app_number] => 12483490 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/483490
Circuit and method for reducing popping sound Jun 11, 2009 Issued
Array ( [id] => 6371269 [patent_doc_number] => 20100315141 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-12-16 [patent_title] => 'MULTIPLE-STAGE, SIGNAL EDGE ALIGNMENT APPARATUS AND METHODS' [patent_app_type] => utility [patent_app_number] => 12/483392 [patent_app_country] => US [patent_app_date] => 2009-06-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 12346 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0315/20100315141.pdf [firstpage_image] =>[orig_patent_app_number] => 12483392 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/483392
Multiple-stage, signal edge alignment apparatus and methods Jun 11, 2009 Issued
Array ( [id] => 6121686 [patent_doc_number] => 20110084741 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-04-14 [patent_title] => 'FAST-LOCKING BANG-BANG PLL WITH LOW OUPUT JITTER' [patent_app_type] => utility [patent_app_number] => 12/999596 [patent_app_country] => US [patent_app_date] => 2009-06-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 4395 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0084/20110084741.pdf [firstpage_image] =>[orig_patent_app_number] => 12999596 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/999596
Fast-locking bang-bang PLL with low ouput jitter Jun 10, 2009 Issued
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