Search

Douglas C. Butler

Examiner (ID: 16249)

Most Active Art Unit
3104
Art Unit(s)
2899, 3683, 3105, 3104, 3613, 3103
Total Applications
3087
Issued Applications
2757
Pending Applications
77
Abandoned Applications
253

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 19979989 [patent_doc_number] => 12347475 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-07-01 [patent_title] => Memory device and method of operating a voltage-controlled magnetic anisotropy (VCMA) magnetic tunnel junction (MTJ) device [patent_app_type] => utility [patent_app_number] => 17/344796 [patent_app_country] => US [patent_app_date] => 2021-06-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 33 [patent_no_of_words] => 5633 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 360 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17344796 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/344796
Memory device and method of operating a voltage-controlled magnetic anisotropy (VCMA) magnetic tunnel junction (MTJ) device Jun 9, 2021 Issued
Array ( [id] => 18890808 [patent_doc_number] => 11869585 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-01-09 [patent_title] => Segregation-based memory [patent_app_type] => utility [patent_app_number] => 17/331610 [patent_app_country] => US [patent_app_date] => 2021-05-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 18330 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17331610 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/331610
Segregation-based memory May 25, 2021 Issued
Array ( [id] => 18669735 [patent_doc_number] => 11776645 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-10-03 [patent_title] => Stacked electronic device capable of retaining an analog potential [patent_app_type] => utility [patent_app_number] => 17/314554 [patent_app_country] => US [patent_app_date] => 2021-05-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 46 [patent_no_of_words] => 19916 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 166 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17314554 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/314554
Stacked electronic device capable of retaining an analog potential May 6, 2021 Issued
Array ( [id] => 17776903 [patent_doc_number] => 20220243252 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-08-04 [patent_title] => ISOTOPE MODIFIED NUCLEOTIDES FOR DNA DATA STORAGE [patent_app_type] => utility [patent_app_number] => 17/308837 [patent_app_country] => US [patent_app_date] => 2021-05-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8466 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 60 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17308837 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/308837
ISOTOPE MODIFIED NUCLEOTIDES FOR DNA DATA STORAGE May 4, 2021 Abandoned
Array ( [id] => 18562720 [patent_doc_number] => 11727970 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-08-15 [patent_title] => Memory device for generating word line signals having varying pulse widths [patent_app_type] => utility [patent_app_number] => 17/246814 [patent_app_country] => US [patent_app_date] => 2021-05-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 15 [patent_no_of_words] => 8304 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17246814 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/246814
Memory device for generating word line signals having varying pulse widths May 2, 2021 Issued
Array ( [id] => 17779876 [patent_doc_number] => 20220246226 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-08-04 [patent_title] => POWER CIRCUIT, ELECTRONIC FUSE CIRCUIT, AND METHOD FOR PROVIDING POWER TO ELECTRONIC FUSE CIRCUIT [patent_app_type] => utility [patent_app_number] => 17/224692 [patent_app_country] => US [patent_app_date] => 2021-04-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5146 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17224692 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/224692
Power circuit, electronic fuse circuit, and method for providing power to electronic fuse circuit Apr 6, 2021 Issued
Array ( [id] => 18423682 [patent_doc_number] => 20230178146 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-06-08 [patent_title] => APPARATUS AND METHOD FOR CHANGING THE FUNCTIONALITY OF AN INTEGRATED CIRCUIT USING CHARGE TRAP TRANSISTORS [patent_app_type] => utility [patent_app_number] => 17/916015 [patent_app_country] => US [patent_app_date] => 2021-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12212 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -27 [patent_words_short_claim] => 49 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17916015 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/916015
APPARATUS AND METHOD FOR CHANGING THE FUNCTIONALITY OF AN INTEGRATED CIRCUIT USING CHARGE TRAP TRANSISTORS Mar 29, 2021 Pending
Array ( [id] => 16951439 [patent_doc_number] => 20210210131 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-07-08 [patent_title] => APPARATUS AND METHOD FOR CONTROLLING ERASING DATA IN FERROELECTRIC MEMORY CELLS [patent_app_type] => utility [patent_app_number] => 17/211556 [patent_app_country] => US [patent_app_date] => 2021-03-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7603 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17211556 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/211556
Apparatus and method for controlling erasing data in ferroelectric memory cells Mar 23, 2021 Issued
Array ( [id] => 18706468 [patent_doc_number] => 11793000 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-10-17 [patent_title] => Circuit and method to enhance efficiency of memory [patent_app_type] => utility [patent_app_number] => 17/200864 [patent_app_country] => US [patent_app_date] => 2021-03-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6179 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17200864 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/200864
Circuit and method to enhance efficiency of memory Mar 13, 2021 Issued
Array ( [id] => 17917172 [patent_doc_number] => 20220319568 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-10-06 [patent_title] => SEMICONDUCTOR MEMORY TRAINING METHODS AND RELATED DEVICES [patent_app_type] => utility [patent_app_number] => 17/310800 [patent_app_country] => US [patent_app_date] => 2021-03-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14650 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 204 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17310800 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/310800
Semiconductor memory training methods and related devices Mar 8, 2021 Issued
Array ( [id] => 17723161 [patent_doc_number] => 20220215883 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-07-07 [patent_title] => THREE-DIMENSIONAL MEMORY DEVICE PROGRAMMING WITH REDUCED THRESHOLD VOLTAGE SHIFT [patent_app_type] => utility [patent_app_number] => 17/186429 [patent_app_country] => US [patent_app_date] => 2021-02-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13029 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 163 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17186429 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/186429
Three-dimensional memory device programming with reduced threshold voltage shift Feb 25, 2021 Issued
Array ( [id] => 17840806 [patent_doc_number] => 20220278112 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-09-01 [patent_title] => MEMORY DEVICE HAVING 2-TRANSISTOR VERTICAL MEMORY CELL AND SHIELD STRUCTURES [patent_app_type] => utility [patent_app_number] => 17/186962 [patent_app_country] => US [patent_app_date] => 2021-02-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16816 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 185 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17186962 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/186962
Memory device having 2-transistor vertical memory cell and shield structures Feb 25, 2021 Issued
Array ( [id] => 17455911 [patent_doc_number] => 11270777 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-03-08 [patent_title] => Memory system capable of reducing the reading time [patent_app_type] => utility [patent_app_number] => 17/187679 [patent_app_country] => US [patent_app_date] => 2021-02-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 3731 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17187679 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/187679
Memory system capable of reducing the reading time Feb 25, 2021 Issued
Array ( [id] => 19108472 [patent_doc_number] => 11961585 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-04-16 [patent_title] => Centralized placement of command and address swapping in memory devices [patent_app_type] => utility [patent_app_number] => 17/185637 [patent_app_country] => US [patent_app_date] => 2021-02-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 7010 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 146 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17185637 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/185637
Centralized placement of command and address swapping in memory devices Feb 24, 2021 Issued
Array ( [id] => 17776902 [patent_doc_number] => 20220243251 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-08-04 [patent_title] => NUCLEOTIDES WITH ISOTOPES FOR DNA DATA STORAGE [patent_app_type] => utility [patent_app_number] => 17/166838 [patent_app_country] => US [patent_app_date] => 2021-02-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7610 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 57 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17166838 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/166838
NUCLEOTIDES WITH ISOTOPES FOR DNA DATA STORAGE Feb 2, 2021 Abandoned
Array ( [id] => 17764547 [patent_doc_number] => 20220238160 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-07-28 [patent_title] => OPERATION METHOD OF MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 17/158035 [patent_app_country] => US [patent_app_date] => 2021-01-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2874 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -9 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17158035 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/158035
OPERATION METHOD OF MEMORY DEVICE Jan 25, 2021 Abandoned
Array ( [id] => 17924679 [patent_doc_number] => 11467928 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-10-11 [patent_title] => Circuit and method for storing information in non-volatile memory during a loss of power event [patent_app_type] => utility [patent_app_number] => 17/150140 [patent_app_country] => US [patent_app_date] => 2021-01-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6901 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17150140 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/150140
Circuit and method for storing information in non-volatile memory during a loss of power event Jan 14, 2021 Issued
Array ( [id] => 17737751 [patent_doc_number] => 20220223213 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-07-14 [patent_title] => POST OVER-ERASE CORRECTION METHOD WITH AUTO-ADJUSTING VERIFICATION AND LEAKAGE DEGREE DETECTION [patent_app_type] => utility [patent_app_number] => 17/149689 [patent_app_country] => US [patent_app_date] => 2021-01-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5535 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -40 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17149689 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/149689
Post over-erase correction method with auto-adjusting verification and leakage degree detection Jan 13, 2021 Issued
Array ( [id] => 17373410 [patent_doc_number] => 20220028462 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-01-27 [patent_title] => MEMORY DEVICE AND OPERATING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 17/145828 [patent_app_country] => US [patent_app_date] => 2021-01-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9247 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17145828 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/145828
Memory device and operating method thereof Jan 10, 2021 Issued
Array ( [id] => 18205214 [patent_doc_number] => 11587616 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-02-21 [patent_title] => Apparatus and method with in-memory processing [patent_app_type] => utility [patent_app_number] => 17/141474 [patent_app_country] => US [patent_app_date] => 2021-01-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 13855 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17141474 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/141474
Apparatus and method with in-memory processing Jan 4, 2021 Issued
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