Douglas D. Watts

Array ( [id] => 5401360 [patent_doc_number] => 20090236673 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-09-24 [patent_title] => 'METHOD FOR SUPPRESSING LAYOUT SENSITIVITY OF THRESHOLD VOLTAGE IN A TRANSISTOR ARRAY' [patent_app_type] => utility [patent_app_number] => 12/464211 [patent_app_country] => US [patent_app_date] => 2009-05-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 2625 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0236/20090236673.pdf [firstpage_image] =>[orig_patent_app_number] => 12464211 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4629262 [patent_doc_number] => 08008148 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-08-30 [patent_title] => 'Method of manufacturing M-I-M capacitor of semiconductor device' [patent_app_type] => utility [patent_app_number] => 12/436890 [patent_app_country] => US [patent_app_date] => 2009-05-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 7 [patent_no_of_words] => 2650 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/008/08008148.pdf [firstpage_image] =>[orig_patent_app_number] => 12436890 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6489218 [patent_doc_number] => 20100285667 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-11-11 [patent_title] => 'METHOD TO PRESERVE THE CRITICAL DIMENSION (CD) OF AN INTERCONNECT STRUCTURE' [patent_app_type] => utility [patent_app_number] => 12/436459 [patent_app_country] => US [patent_app_date] => 2009-05-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5430 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0285/20100285667.pdf [firstpage_image] =>[orig_patent_app_number] => 12436459 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5313542 [patent_doc_number] => 20090278140 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-11-12 [patent_title] => 'MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 12/433179 [patent_app_country] => US [patent_app_date] => 2009-04-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2978 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0278/20090278140.pdf [firstpage_image] =>[orig_patent_app_number] => 12433179 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4644329 [patent_doc_number] => 08021934 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-09-20 [patent_title] => 'Method for making a transistor with metallic source and drain' [patent_app_type] => utility [patent_app_number] => 12/433209 [patent_app_country] => US [patent_app_date] => 2009-04-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 13 [patent_no_of_words] => 4589 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 30 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/021/08021934.pdf [firstpage_image] =>[orig_patent_app_number] => 12433209 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5555546 [patent_doc_number] => 20090267123 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-10-29 [patent_title] => 'SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 12/426509 [patent_app_country] => US [patent_app_date] => 2009-04-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 4903 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0267/20090267123.pdf [firstpage_image] =>[orig_patent_app_number] => 12426509 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4517688 [patent_doc_number] => 07932537 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-04-26 [patent_title] => 'Process-variation tolerant diode, standard cells including the same, tags and sensors containing the same, and methods for manufacturing the same' [patent_app_type] => utility [patent_app_number] => 12/424509 [patent_app_country] => US [patent_app_date] => 2009-04-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 16 [patent_no_of_words] => 9168 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/932/07932537.pdf [firstpage_image] =>[orig_patent_app_number] => 12424509 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6484900 [patent_doc_number] => 20100258928 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-10-14 [patent_title] => 'INTEGRATED CIRCUIT PACKAGING SYSTEM WITH STACKED INTEGRATED CIRCUIT AND METHOD OF MANUFACTURE THEREOF' [patent_app_type] => utility [patent_app_number] => 12/423099 [patent_app_country] => US [patent_app_date] => 2009-04-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5299 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0258/20100258928.pdf [firstpage_image] =>[orig_patent_app_number] => 12423099 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 210438 [patent_doc_number] => 07625799 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-12-01 [patent_title] => 'Method of forming a shielded gate field effect transistor' [patent_app_type] => utility [patent_app_number] => 12/418949 [patent_app_country] => US [patent_app_date] => 2009-04-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 42 [patent_no_of_words] => 7377 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 176 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/625/07625799.pdf [firstpage_image] =>[orig_patent_app_number] => 12418949 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5379880 [patent_doc_number] => 20090191719 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-07-30 [patent_title] => 'METHODS FOR FABRICATING COMPOUND MATERIAL WAFERS' [patent_app_type] => utility [patent_app_number] => 12/415085 [patent_app_country] => US [patent_app_date] => 2009-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 4833 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0191/20090191719.pdf [firstpage_image] =>[orig_patent_app_number] => 12415085 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8994938 [patent_doc_number] => 08518822 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-08-27 [patent_title] => 'Integrated circuit packaging system with multi-stacked flip chips and method of manufacture thereof' [patent_app_type] => utility [patent_app_number] => 12/411390 [patent_app_country] => US [patent_app_date] => 2009-03-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 22 [patent_no_of_words] => 4596 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 48 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12411390 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7998065 [patent_doc_number] => 08080880 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-12-20 [patent_title] => 'Semiconductor device with arrangement of parallel conductor lines being insulated, between and orthogonal to external contact pads' [patent_app_type] => utility [patent_app_number] => 12/408110 [patent_app_country] => US [patent_app_date] => 2009-03-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 30 [patent_no_of_words] => 5029 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/080/08080880.pdf [firstpage_image] =>[orig_patent_app_number] => 12408110 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5340536 [patent_doc_number] => 20090179186 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-07-16 [patent_title] => 'Phase change memory cells delineated by regions of modified film resistivity' [patent_app_type] => utility [patent_app_number] => 12/407068 [patent_app_country] => US [patent_app_date] => 2009-03-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 8283 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0179/20090179186.pdf [firstpage_image] =>[orig_patent_app_number] => 12407068 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5353004 [patent_doc_number] => 20090184348 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-07-23 [patent_title] => 'Slim Spacer Implementation to Improve Drive Current' [patent_app_type] => utility [patent_app_number] => 12/372868 [patent_app_country] => US [patent_app_date] => 2009-02-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 3653 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0184/20090184348.pdf [firstpage_image] =>[orig_patent_app_number] => 12372868 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6513921 [patent_doc_number] => 20100202631 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-08-12 [patent_title] => 'Adjusting Dynamic Range for Audio Reproduction' [patent_app_type] => utility [patent_app_number] => 12/367095 [patent_app_country] => US [patent_app_date] => 2009-02-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 8813 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0202/20100202631.pdf [firstpage_image] =>[orig_patent_app_number] => 12367095 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6571185 [patent_doc_number] => 20100046772 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-02-25 [patent_title] => 'SOUND LEVEL CONTROL' [patent_app_type] => utility [patent_app_number] => 12/367232 [patent_app_country] => US [patent_app_date] => 2009-02-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4982 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0046/20100046772.pdf [firstpage_image] =>[orig_patent_app_number] => 12367232 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5526363 [patent_doc_number] => 20090196440 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-08-06 [patent_title] => 'AUDIO PLAYER APPARATUS AND ITS CONTROL METHOD' [patent_app_type] => utility [patent_app_number] => 12/365453 [patent_app_country] => US [patent_app_date] => 2009-02-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 4106 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0196/20090196440.pdf [firstpage_image] =>[orig_patent_app_number] => 12365453 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4382 [patent_doc_number] => 07811863 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2010-10-12 [patent_title] => 'Method of making a semiconductor chip assembly with metal pillar and encapsulant grinding and heat sink attachment' [patent_app_type] => utility [patent_app_number] => 12/363765 [patent_app_country] => US [patent_app_date] => 2009-02-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 48 [patent_figures_cnt] => 144 [patent_no_of_words] => 30145 [patent_no_of_claims] => 100 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 332 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/811/07811863.pdf [firstpage_image] =>[orig_patent_app_number] => 12363765 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9469641 [patent_doc_number] => 08723275 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-05-13 [patent_title] => 'Semiconductor device with metal silicides having different phases' [patent_app_type] => utility [patent_app_number] => 12/322118 [patent_app_country] => US [patent_app_date] => 2009-01-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 1858 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12322118 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5278682 [patent_doc_number] => 20090130814 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-05-21 [patent_title] => 'SEMICONDUCTOR METHODS' [patent_app_type] => utility [patent_app_number] => 12/357661 [patent_app_country] => US [patent_app_date] => 2009-01-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 26 [patent_no_of_words] => 13622 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0130/20090130814.pdf [firstpage_image] =>[orig_patent_app_number] => 12357661 [rel_patent_id] =>[rel_patent_doc_number] =>)