Search

Douglas D. Watts

Examiner (ID: 17148)

Most Active Art Unit
3204
Art Unit(s)
3724, 3203, 3101, 2899, 2902, 3204, 3103, 3105, 3727
Total Applications
2654
Issued Applications
2350
Pending Applications
81
Abandoned Applications
222

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4756715 [patent_doc_number] => 20080308940 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-12-18 [patent_title] => 'LATERAL CURRENT CARRYING CAPABILITY IMPROVEMENT IN SEMICONDUCTOR DEVICES' [patent_app_type] => utility [patent_app_number] => 12/198196 [patent_app_country] => US [patent_app_date] => 2008-08-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 3718 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0308/20080308940.pdf [firstpage_image] =>[orig_patent_app_number] => 12198196 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/198196
LATERAL CURRENT CARRYING CAPABILITY IMPROVEMENT IN SEMICONDUCTOR DEVICES Aug 25, 2008 Abandoned
Array ( [id] => 5319680 [patent_doc_number] => 20090057670 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-03-05 [patent_title] => 'Semiconductor Device and Process for Production Thereof' [patent_app_type] => utility [patent_app_number] => 12/193900 [patent_app_country] => US [patent_app_date] => 2008-08-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 17804 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0057/20090057670.pdf [firstpage_image] =>[orig_patent_app_number] => 12193900 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/193900
Semiconductor device and process for production thereof Aug 18, 2008 Issued
Array ( [id] => 6632229 [patent_doc_number] => 20100035393 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-02-11 [patent_title] => 'METHOD FOR FABRICATING SEMICONDUCTOR DEVICE HAVING RADIATION HARDENED INSULATORS' [patent_app_type] => utility [patent_app_number] => 12/186750 [patent_app_country] => US [patent_app_date] => 2008-08-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2281 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0035/20100035393.pdf [firstpage_image] =>[orig_patent_app_number] => 12186750 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/186750
Method for fabricating semiconductor device having radiation hardened insulators Aug 5, 2008 Issued
Array ( [id] => 4469451 [patent_doc_number] => 07943482 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-05-17 [patent_title] => 'Method for semiconductor device having radiation hardened insulators and design structure thereof' [patent_app_type] => utility [patent_app_number] => 12/186762 [patent_app_country] => US [patent_app_date] => 2008-08-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3079 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/943/07943482.pdf [firstpage_image] =>[orig_patent_app_number] => 12186762 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/186762
Method for semiconductor device having radiation hardened insulators and design structure thereof Aug 5, 2008 Issued
Array ( [id] => 4708107 [patent_doc_number] => 20080296633 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-12-04 [patent_title] => 'ELECTRONIC DEVICE INCLUDING A TRANSISTOR STRUCTURE HAVING AN ACTIVE REGION ADJACENT TO A STRESSOR LAYER' [patent_app_type] => utility [patent_app_number] => 12/180818 [patent_app_country] => US [patent_app_date] => 2008-07-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 8091 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0296/20080296633.pdf [firstpage_image] =>[orig_patent_app_number] => 12180818 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/180818
Electronic device including a transistor structure having an active region adjacent to a stressor layer Jul 27, 2008 Issued
Array ( [id] => 5445245 [patent_doc_number] => 20090046471 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-02-19 [patent_title] => 'Display panel with improved reflectivity' [patent_app_type] => utility [patent_app_number] => 12/216643 [patent_app_country] => US [patent_app_date] => 2008-07-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 14585 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0046/20090046471.pdf [firstpage_image] =>[orig_patent_app_number] => 12216643 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/216643
Display panel with improved reflectivity Jul 8, 2008 Abandoned
Array ( [id] => 4610486 [patent_doc_number] => 07994623 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-08-09 [patent_title] => 'Semiconductor device with offset stacked integrated circuits' [patent_app_type] => utility [patent_app_number] => 12/167228 [patent_app_country] => US [patent_app_date] => 2008-07-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 34 [patent_no_of_words] => 12252 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 322 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/994/07994623.pdf [firstpage_image] =>[orig_patent_app_number] => 12167228 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/167228
Semiconductor device with offset stacked integrated circuits Jul 1, 2008 Issued
Array ( [id] => 5465192 [patent_doc_number] => 20090325392 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-12-31 [patent_title] => 'SUB-SECOND ANNEALING PROCESSES FOR SEMICONDUCTOR DEVICES' [patent_app_type] => utility [patent_app_number] => 12/164560 [patent_app_country] => US [patent_app_date] => 2008-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3385 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0325/20090325392.pdf [firstpage_image] =>[orig_patent_app_number] => 12164560 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/164560
Sub-second annealing processes for semiconductor devices Jun 29, 2008 Issued
Array ( [id] => 4887061 [patent_doc_number] => 20080261393 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-10-23 [patent_title] => 'REDUCING WIRE EROSION DURING DAMASCENE PROCESSING' [patent_app_type] => utility [patent_app_number] => 12/142094 [patent_app_country] => US [patent_app_date] => 2008-06-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4005 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0261/20080261393.pdf [firstpage_image] =>[orig_patent_app_number] => 12142094 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/142094
Reducing wire erosion during damascene processing Jun 18, 2008 Issued
Array ( [id] => 5295365 [patent_doc_number] => 20090010291 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-01-08 [patent_title] => 'Light-emitting device with a protection layer to prevent the inter-diffusion of zinc (Zn) atoms' [patent_app_type] => utility [patent_app_number] => 12/213392 [patent_app_country] => US [patent_app_date] => 2008-06-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 4655 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0010/20090010291.pdf [firstpage_image] =>[orig_patent_app_number] => 12213392 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/213392
Light-emitting device with a protection layer to prevent the inter-diffusion of zinc (Zn) atoms Jun 17, 2008 Issued
Array ( [id] => 326551 [patent_doc_number] => 07514322 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-04-07 [patent_title] => 'Shielded gate field effect transistor' [patent_app_type] => utility [patent_app_number] => 12/125242 [patent_app_country] => US [patent_app_date] => 2008-05-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 42 [patent_no_of_words] => 7391 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 176 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/514/07514322.pdf [firstpage_image] =>[orig_patent_app_number] => 12125242 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/125242
Shielded gate field effect transistor May 21, 2008 Issued
Array ( [id] => 4711216 [patent_doc_number] => 20080299742 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-12-04 [patent_title] => 'Method for manufacturing SOI wafer' [patent_app_type] => utility [patent_app_number] => 12/153519 [patent_app_country] => US [patent_app_date] => 2008-05-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 7627 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0299/20080299742.pdf [firstpage_image] =>[orig_patent_app_number] => 12153519 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/153519
Method for reducing the thickness of an SOI layer May 19, 2008 Issued
Array ( [id] => 263656 [patent_doc_number] => 07569420 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-08-04 [patent_title] => 'Flip-chip packaging method for light emitting diode with eutectic layer not overlapping insulating layer' [patent_app_type] => utility [patent_app_number] => 12/116950 [patent_app_country] => US [patent_app_date] => 2008-05-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 1846 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/569/07569420.pdf [firstpage_image] =>[orig_patent_app_number] => 12116950 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/116950
Flip-chip packaging method for light emitting diode with eutectic layer not overlapping insulating layer May 6, 2008 Issued
Array ( [id] => 5572936 [patent_doc_number] => 20090140297 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-06-04 [patent_title] => 'SELF-ALIGNMENT SCHEME FOR A HETEROJUNCTION BIPOLAR TRANSISTOR' [patent_app_type] => utility [patent_app_number] => 12/114036 [patent_app_country] => US [patent_app_date] => 2008-05-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 3855 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0140/20090140297.pdf [firstpage_image] =>[orig_patent_app_number] => 12114036 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/114036
SELF-ALIGNMENT SCHEME FOR A HETEROJUNCTION BIPOLAR TRANSISTOR May 1, 2008 Abandoned
Array ( [id] => 4613010 [patent_doc_number] => 07989358 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-08-02 [patent_title] => 'Prevention of backside cracks in semiconductor chips or wafers using backside film or backside wet etch' [patent_app_type] => utility [patent_app_number] => 12/107303 [patent_app_country] => US [patent_app_date] => 2008-04-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 6 [patent_no_of_words] => 2850 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 160 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/989/07989358.pdf [firstpage_image] =>[orig_patent_app_number] => 12107303 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/107303
Prevention of backside cracks in semiconductor chips or wafers using backside film or backside wet etch Apr 21, 2008 Issued
Array ( [id] => 4570580 [patent_doc_number] => 07847368 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-12-07 [patent_title] => 'Multilayer film with stack of nanometer-scale thicknesses' [patent_app_type] => utility [patent_app_number] => 12/104252 [patent_app_country] => US [patent_app_date] => 2008-04-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 16 [patent_no_of_words] => 3657 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/847/07847368.pdf [firstpage_image] =>[orig_patent_app_number] => 12104252 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/104252
Multilayer film with stack of nanometer-scale thicknesses Apr 15, 2008 Issued
Array ( [id] => 6419602 [patent_doc_number] => 20100167556 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-07-01 [patent_title] => 'THREE DEGREE OF MOVEMENT MOVER AND METHOD FOR CONTROLLING A THREE DEGREE OF MOVEMENT MOVER' [patent_app_type] => utility [patent_app_number] => 12/596569 [patent_app_country] => US [patent_app_date] => 2008-04-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 10326 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0167/20100167556.pdf [firstpage_image] =>[orig_patent_app_number] => 12596569 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/596569
THREE DEGREE OF MOVEMENT MOVER AND METHOD FOR CONTROLLING A THREE DEGREE OF MOVEMENT MOVER Apr 15, 2008 Abandoned
Array ( [id] => 63635 [patent_doc_number] => 07759173 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-07-20 [patent_title] => 'Methods for charge dissipation in integrated circuits' [patent_app_type] => utility [patent_app_number] => 12/103212 [patent_app_country] => US [patent_app_date] => 2008-04-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 15 [patent_no_of_words] => 7008 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 289 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/759/07759173.pdf [firstpage_image] =>[orig_patent_app_number] => 12103212 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/103212
Methods for charge dissipation in integrated circuits Apr 14, 2008 Issued
Array ( [id] => 7527388 [patent_doc_number] => 08043980 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-10-25 [patent_title] => 'Methods for making and using halosilylgermanes' [patent_app_type] => utility [patent_app_number] => 12/594250 [patent_app_country] => US [patent_app_date] => 2008-04-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 32144 [patent_no_of_claims] => 76 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 39 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/043/08043980.pdf [firstpage_image] =>[orig_patent_app_number] => 12594250 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/594250
Methods for making and using halosilylgermanes Apr 1, 2008 Issued
Array ( [id] => 5556 [patent_doc_number] => 07812443 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-10-12 [patent_title] => 'Power semiconductor module for inverter circuit system' [patent_app_type] => utility [patent_app_number] => 12/060629 [patent_app_country] => US [patent_app_date] => 2008-04-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 36 [patent_figures_cnt] => 44 [patent_no_of_words] => 25416 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 169 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/812/07812443.pdf [firstpage_image] =>[orig_patent_app_number] => 12060629 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/060629
Power semiconductor module for inverter circuit system Mar 31, 2008 Issued
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