Search

Douglas D. Watts

Examiner (ID: 17148)

Most Active Art Unit
3204
Art Unit(s)
3724, 3203, 3101, 2899, 2902, 3204, 3103, 3105, 3727
Total Applications
2654
Issued Applications
2350
Pending Applications
81
Abandoned Applications
222

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4820704 [patent_doc_number] => 20080122000 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-05-29 [patent_title] => 'Strained semiconductor device and method of making same' [patent_app_type] => utility [patent_app_number] => 11/521804 [patent_app_country] => US [patent_app_date] => 2006-09-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4278 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0122/20080122000.pdf [firstpage_image] =>[orig_patent_app_number] => 11521804 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/521804
Strained semiconductor device and method of making same Sep 14, 2006 Issued
Array ( [id] => 5236603 [patent_doc_number] => 20070128760 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-06-07 [patent_title] => 'Process-variation tolerant diode, standard cells including the same, tags and sensors containing the same, and methods for manufacturing the same' [patent_app_type] => utility [patent_app_number] => 11/521924 [patent_app_country] => US [patent_app_date] => 2006-09-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 9218 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0128/20070128760.pdf [firstpage_image] =>[orig_patent_app_number] => 11521924 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/521924
Method of manufacturing complementary diodes Sep 14, 2006 Issued
Array ( [id] => 8772357 [patent_doc_number] => 08426312 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-04-23 [patent_title] => 'Method of reducing contamination by providing an etch stop layer at the substrate edge' [patent_app_type] => utility [patent_app_number] => 11/531793 [patent_app_country] => US [patent_app_date] => 2006-09-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 7233 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 227 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 11531793 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/531793
Method of reducing contamination by providing an etch stop layer at the substrate edge Sep 13, 2006 Issued
Array ( [id] => 817048 [patent_doc_number] => 07410856 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-08-12 [patent_title] => 'Methods of forming vertical transistors' [patent_app_type] => utility [patent_app_number] => 11/522144 [patent_app_country] => US [patent_app_date] => 2006-09-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 21 [patent_no_of_words] => 5299 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 238 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/410/07410856.pdf [firstpage_image] =>[orig_patent_app_number] => 11522144 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/522144
Methods of forming vertical transistors Sep 13, 2006 Issued
Array ( [id] => 5055494 [patent_doc_number] => 20070058415 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-03-15 [patent_title] => 'Method for depositing ferroelectric thin films using a mixed oxidant gas' [patent_app_type] => utility [patent_app_number] => 11/520623 [patent_app_country] => US [patent_app_date] => 2006-09-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 7057 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0058/20070058415.pdf [firstpage_image] =>[orig_patent_app_number] => 11520623 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/520623
Method for depositing ferroelectric thin films using a mixed oxidant gas Sep 13, 2006 Abandoned
Array ( [id] => 5171991 [patent_doc_number] => 20070072424 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-03-29 [patent_title] => 'Method of manufacturing silicon rich oxide (SRO) and semiconductor device employing SRO' [patent_app_type] => utility [patent_app_number] => 11/519083 [patent_app_country] => US [patent_app_date] => 2006-09-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 4985 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0072/20070072424.pdf [firstpage_image] =>[orig_patent_app_number] => 11519083 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/519083
Method of manufacturing silicon rich oxide (SRO) and semiconductor device employing SRO Sep 11, 2006 Issued
Array ( [id] => 123941 [patent_doc_number] => 07705342 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-04-27 [patent_title] => 'Porous semiconductor-based evaporator having porous and non-porous regions, the porous regions having through-holes' [patent_app_type] => utility [patent_app_number] => 11/530107 [patent_app_country] => US [patent_app_date] => 2006-09-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 32 [patent_no_of_words] => 9347 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/705/07705342.pdf [firstpage_image] =>[orig_patent_app_number] => 11530107 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/530107
Porous semiconductor-based evaporator having porous and non-porous regions, the porous regions having through-holes Sep 7, 2006 Issued
Array ( [id] => 817055 [patent_doc_number] => 07410863 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-08-12 [patent_title] => 'Methods of forming and using memory cell structures' [patent_app_type] => utility [patent_app_number] => 11/516730 [patent_app_country] => US [patent_app_date] => 2006-09-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 2000 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/410/07410863.pdf [firstpage_image] =>[orig_patent_app_number] => 11516730 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/516730
Methods of forming and using memory cell structures Sep 6, 2006 Issued
Array ( [id] => 432270 [patent_doc_number] => 07265043 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-09-04 [patent_title] => 'Methods for making microwave circuits' [patent_app_type] => utility [patent_app_number] => 11/510102 [patent_app_country] => US [patent_app_date] => 2006-08-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 16 [patent_no_of_words] => 4509 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/265/07265043.pdf [firstpage_image] =>[orig_patent_app_number] => 11510102 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/510102
Methods for making microwave circuits Aug 24, 2006 Issued
Array ( [id] => 4829336 [patent_doc_number] => 20080128838 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-06-05 [patent_title] => 'SENSOR MODULE AND METHOD OF MANUFACTURING SAME' [patent_app_type] => utility [patent_app_number] => 11/467474 [patent_app_country] => US [patent_app_date] => 2006-08-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 9975 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0128/20080128838.pdf [firstpage_image] =>[orig_patent_app_number] => 11467474 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/467474
Sensor module and method of manufacturing same Aug 24, 2006 Issued
Array ( [id] => 5688455 [patent_doc_number] => 20060286770 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-12-21 [patent_title] => 'Method for concurrently producing at least a pair of semiconductor structures that each include at least one useful layer on a substrate' [patent_app_type] => utility [patent_app_number] => 11/509047 [patent_app_country] => US [patent_app_date] => 2006-08-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5049 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0286/20060286770.pdf [firstpage_image] =>[orig_patent_app_number] => 11509047 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/509047
Method for concurrently producing at least a pair of semiconductor structures that each include at least one useful layer on a substrate Aug 23, 2006 Issued
Array ( [id] => 4669912 [patent_doc_number] => 20080044972 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-02-21 [patent_title] => 'Methods of Forming Nonvolatile Memories with Shaped Floating Gates' [patent_app_type] => utility [patent_app_number] => 11/465038 [patent_app_country] => US [patent_app_date] => 2006-08-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 7732 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0044/20080044972.pdf [firstpage_image] =>[orig_patent_app_number] => 11465038 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/465038
Methods of forming nonvolatile memories with L-shaped floating gates Aug 15, 2006 Issued
Array ( [id] => 7740413 [patent_doc_number] => 08105955 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-01-31 [patent_title] => 'Integrated circuit system with carbon and non-carbon silicon' [patent_app_type] => utility [patent_app_number] => 11/464664 [patent_app_country] => US [patent_app_date] => 2006-08-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 7 [patent_no_of_words] => 2955 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/105/08105955.pdf [firstpage_image] =>[orig_patent_app_number] => 11464664 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/464664
Integrated circuit system with carbon and non-carbon silicon Aug 14, 2006 Issued
Array ( [id] => 4820588 [patent_doc_number] => 20080121920 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-05-29 [patent_title] => 'Flip-Chip Packaging Structure for Light Emitting Diode and Method Thereof' [patent_app_type] => utility [patent_app_number] => 11/463273 [patent_app_country] => US [patent_app_date] => 2006-08-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 1810 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0121/20080121920.pdf [firstpage_image] =>[orig_patent_app_number] => 11463273 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/463273
Flip-chip packaging structure for light emitting diode and method thereof Aug 7, 2006 Issued
Array ( [id] => 4825903 [patent_doc_number] => 20080124858 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-05-29 [patent_title] => 'SELECTIVE STRESS RELAXATION BY AMORPHIZING IMPLANT IN STRAINED SILICON ON INSULATOR INTEGRATED CIRCUIT' [patent_app_type] => utility [patent_app_number] => 11/462773 [patent_app_country] => US [patent_app_date] => 2006-08-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3818 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0124/20080124858.pdf [firstpage_image] =>[orig_patent_app_number] => 11462773 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/462773
SELECTIVE STRESS RELAXATION BY AMORPHIZING IMPLANT IN STRAINED SILICON ON INSULATOR INTEGRATED CIRCUIT Aug 6, 2006 Abandoned
Array ( [id] => 5605554 [patent_doc_number] => 20060267070 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-11-30 [patent_title] => 'Gate coupling in floating-gate memory cells' [patent_app_type] => utility [patent_app_number] => 11/499192 [patent_app_country] => US [patent_app_date] => 2006-08-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3251 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0267/20060267070.pdf [firstpage_image] =>[orig_patent_app_number] => 11499192 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/499192
Gate coupling in floating-gate memory cells Aug 3, 2006 Abandoned
Array ( [id] => 823587 [patent_doc_number] => 07405139 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-07-29 [patent_title] => 'Prevention of backside cracks in semiconductor chips or wafers using backside film or backside wet etch' [patent_app_type] => utility [patent_app_number] => 11/462124 [patent_app_country] => US [patent_app_date] => 2006-08-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 6 [patent_no_of_words] => 2814 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/405/07405139.pdf [firstpage_image] =>[orig_patent_app_number] => 11462124 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/462124
Prevention of backside cracks in semiconductor chips or wafers using backside film or backside wet etch Aug 2, 2006 Issued
Array ( [id] => 4999932 [patent_doc_number] => 20070042566 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-02-22 [patent_title] => 'STRAINED SILICON ON INSULATOR (SSOI) STRUCTURE WITH IMPROVED CRYSTALLINITY IN THE STRAINED SILICON LAYER' [patent_app_type] => utility [patent_app_number] => 11/461653 [patent_app_country] => US [patent_app_date] => 2006-08-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 8445 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0042/20070042566.pdf [firstpage_image] =>[orig_patent_app_number] => 11461653 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/461653
STRAINED SILICON ON INSULATOR (SSOI) STRUCTURE WITH IMPROVED CRYSTALLINITY IN THE STRAINED SILICON LAYER Jul 31, 2006 Abandoned
Array ( [id] => 4826006 [patent_doc_number] => 20080124912 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-05-29 [patent_title] => 'SEMICONDUCTOR METHODS' [patent_app_type] => utility [patent_app_number] => 11/461673 [patent_app_country] => US [patent_app_date] => 2006-08-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 26 [patent_no_of_words] => 13396 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0124/20080124912.pdf [firstpage_image] =>[orig_patent_app_number] => 11461673 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/461673
SEMICONDUCTOR METHODS Jul 31, 2006 Abandoned
Array ( [id] => 4820834 [patent_doc_number] => 20080122096 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-05-29 [patent_title] => 'METHODS FOR LATERAL CURRENT CARRYING CAPABILITY IMPROVEMENT IN SEMICONDUCTOR DEVICES' [patent_app_type] => utility [patent_app_number] => 11/460314 [patent_app_country] => US [patent_app_date] => 2006-07-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 4087 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0122/20080122096.pdf [firstpage_image] =>[orig_patent_app_number] => 11460314 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/460314
Methods for lateral current carrying capability improvement in semiconductor devices Jul 26, 2006 Issued
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