Search

Douglas King

Examiner (ID: 15404, Phone: (571)272-2311 , Office: P/2824 )

Most Active Art Unit
2824
Art Unit(s)
2824
Total Applications
1004
Issued Applications
774
Pending Applications
71
Abandoned Applications
171

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 18706468 [patent_doc_number] => 11793000 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-10-17 [patent_title] => Circuit and method to enhance efficiency of memory [patent_app_type] => utility [patent_app_number] => 17/200864 [patent_app_country] => US [patent_app_date] => 2021-03-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6179 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17200864 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/200864
Circuit and method to enhance efficiency of memory Mar 13, 2021 Issued
Array ( [id] => 17917172 [patent_doc_number] => 20220319568 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-10-06 [patent_title] => SEMICONDUCTOR MEMORY TRAINING METHODS AND RELATED DEVICES [patent_app_type] => utility [patent_app_number] => 17/310800 [patent_app_country] => US [patent_app_date] => 2021-03-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14650 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 204 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17310800 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/310800
Semiconductor memory training methods and related devices Mar 8, 2021 Issued
Array ( [id] => 17723161 [patent_doc_number] => 20220215883 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-07-07 [patent_title] => THREE-DIMENSIONAL MEMORY DEVICE PROGRAMMING WITH REDUCED THRESHOLD VOLTAGE SHIFT [patent_app_type] => utility [patent_app_number] => 17/186429 [patent_app_country] => US [patent_app_date] => 2021-02-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13029 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 163 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17186429 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/186429
Three-dimensional memory device programming with reduced threshold voltage shift Feb 25, 2021 Issued
Array ( [id] => 17840806 [patent_doc_number] => 20220278112 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-09-01 [patent_title] => MEMORY DEVICE HAVING 2-TRANSISTOR VERTICAL MEMORY CELL AND SHIELD STRUCTURES [patent_app_type] => utility [patent_app_number] => 17/186962 [patent_app_country] => US [patent_app_date] => 2021-02-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16816 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 185 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17186962 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/186962
Memory device having 2-transistor vertical memory cell and shield structures Feb 25, 2021 Issued
Array ( [id] => 17455911 [patent_doc_number] => 11270777 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-03-08 [patent_title] => Memory system capable of reducing the reading time [patent_app_type] => utility [patent_app_number] => 17/187679 [patent_app_country] => US [patent_app_date] => 2021-02-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 3731 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17187679 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/187679
Memory system capable of reducing the reading time Feb 25, 2021 Issued
Array ( [id] => 19108472 [patent_doc_number] => 11961585 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-04-16 [patent_title] => Centralized placement of command and address swapping in memory devices [patent_app_type] => utility [patent_app_number] => 17/185637 [patent_app_country] => US [patent_app_date] => 2021-02-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 7010 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 146 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17185637 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/185637
Centralized placement of command and address swapping in memory devices Feb 24, 2021 Issued
Array ( [id] => 17776902 [patent_doc_number] => 20220243251 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-08-04 [patent_title] => NUCLEOTIDES WITH ISOTOPES FOR DNA DATA STORAGE [patent_app_type] => utility [patent_app_number] => 17/166838 [patent_app_country] => US [patent_app_date] => 2021-02-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7610 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 57 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17166838 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/166838
NUCLEOTIDES WITH ISOTOPES FOR DNA DATA STORAGE Feb 2, 2021 Abandoned
Array ( [id] => 17764547 [patent_doc_number] => 20220238160 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-07-28 [patent_title] => OPERATION METHOD OF MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 17/158035 [patent_app_country] => US [patent_app_date] => 2021-01-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2874 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -9 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17158035 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/158035
OPERATION METHOD OF MEMORY DEVICE Jan 25, 2021 Abandoned
Array ( [id] => 17924679 [patent_doc_number] => 11467928 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-10-11 [patent_title] => Circuit and method for storing information in non-volatile memory during a loss of power event [patent_app_type] => utility [patent_app_number] => 17/150140 [patent_app_country] => US [patent_app_date] => 2021-01-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6901 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17150140 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/150140
Circuit and method for storing information in non-volatile memory during a loss of power event Jan 14, 2021 Issued
Array ( [id] => 17737751 [patent_doc_number] => 20220223213 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-07-14 [patent_title] => POST OVER-ERASE CORRECTION METHOD WITH AUTO-ADJUSTING VERIFICATION AND LEAKAGE DEGREE DETECTION [patent_app_type] => utility [patent_app_number] => 17/149689 [patent_app_country] => US [patent_app_date] => 2021-01-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5535 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -40 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17149689 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/149689
Post over-erase correction method with auto-adjusting verification and leakage degree detection Jan 13, 2021 Issued
Array ( [id] => 17373410 [patent_doc_number] => 20220028462 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-01-27 [patent_title] => MEMORY DEVICE AND OPERATING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 17/145828 [patent_app_country] => US [patent_app_date] => 2021-01-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9247 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17145828 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/145828
Memory device and operating method thereof Jan 10, 2021 Issued
Array ( [id] => 18205214 [patent_doc_number] => 11587616 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-02-21 [patent_title] => Apparatus and method with in-memory processing [patent_app_type] => utility [patent_app_number] => 17/141474 [patent_app_country] => US [patent_app_date] => 2021-01-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 13855 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17141474 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/141474
Apparatus and method with in-memory processing Jan 4, 2021 Issued
Array ( [id] => 18304237 [patent_doc_number] => 11626149 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-04-11 [patent_title] => SPI NOR memory with optimized read and program operation [patent_app_type] => utility [patent_app_number] => 17/137321 [patent_app_country] => US [patent_app_date] => 2020-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 3507 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17137321 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/137321
SPI NOR memory with optimized read and program operation Dec 28, 2020 Issued
Array ( [id] => 18357681 [patent_doc_number] => 11646087 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-05-09 [patent_title] => Nonvolatile memory device, storage device including nonvolatile memory device, and operating method of nonvolatile memory device [patent_app_type] => utility [patent_app_number] => 17/134968 [patent_app_country] => US [patent_app_date] => 2020-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 12482 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 205 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17134968 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/134968
Nonvolatile memory device, storage device including nonvolatile memory device, and operating method of nonvolatile memory device Dec 27, 2020 Issued
Array ( [id] => 17224465 [patent_doc_number] => 11176973 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-11-16 [patent_title] => Apparatuses including input buffers and methods for operating input buffers [patent_app_type] => utility [patent_app_number] => 17/133480 [patent_app_country] => US [patent_app_date] => 2020-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 8610 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17133480 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/133480
Apparatuses including input buffers and methods for operating input buffers Dec 22, 2020 Issued
Array ( [id] => 18527579 [patent_doc_number] => 11714570 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-08-01 [patent_title] => Computing-in-memory device and method [patent_app_type] => utility [patent_app_number] => 17/130918 [patent_app_country] => US [patent_app_date] => 2020-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 3580 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17130918 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/130918
Computing-in-memory device and method Dec 21, 2020 Issued
Array ( [id] => 17691890 [patent_doc_number] => 20220199183 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-06-23 [patent_title] => GENERATION OF PROGRAMMING PARAMETERS FOR NON-VOLATILE MEMORY DEVICE BASED ON PHYSICAL DEVICE PARAMETERS [patent_app_type] => utility [patent_app_number] => 17/131509 [patent_app_country] => US [patent_app_date] => 2020-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11060 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 41 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17131509 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/131509
Generation of programming parameters for non-volatile memory device based on physical device parameters Dec 21, 2020 Issued
Array ( [id] => 17606915 [patent_doc_number] => 11335407 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2022-05-17 [patent_title] => One-ladder read of memory cells coarsely programmed via interleaved two-pass data programming techniques [patent_app_type] => utility [patent_app_number] => 17/127502 [patent_app_country] => US [patent_app_date] => 2020-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 17470 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 220 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17127502 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/127502
One-ladder read of memory cells coarsely programmed via interleaved two-pass data programming techniques Dec 17, 2020 Issued
Array ( [id] => 17825574 [patent_doc_number] => 11430526 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-08-30 [patent_title] => Interleaved two-pass data programming techniques with reduced write amplification [patent_app_type] => utility [patent_app_number] => 17/127413 [patent_app_country] => US [patent_app_date] => 2020-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 11723 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 188 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17127413 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/127413
Interleaved two-pass data programming techniques with reduced write amplification Dec 17, 2020 Issued
Array ( [id] => 17908405 [patent_doc_number] => 11462265 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-10-04 [patent_title] => Reading memory cells coarsely programmed via interleaved two-pass data programming techniques [patent_app_type] => utility [patent_app_number] => 17/127459 [patent_app_country] => US [patent_app_date] => 2020-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 17114 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 164 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17127459 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/127459
Reading memory cells coarsely programmed via interleaved two-pass data programming techniques Dec 17, 2020 Issued
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