
Douglas King
Examiner (ID: 15404, Phone: (571)272-2311 , Office: P/2824 )
| Most Active Art Unit | 2824 |
| Art Unit(s) | 2824 |
| Total Applications | 1004 |
| Issued Applications | 774 |
| Pending Applications | 71 |
| Abandoned Applications | 171 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 17606915
[patent_doc_number] => 11335407
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2022-05-17
[patent_title] => One-ladder read of memory cells coarsely programmed via interleaved two-pass data programming techniques
[patent_app_type] => utility
[patent_app_number] => 17/127502
[patent_app_country] => US
[patent_app_date] => 2020-12-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
[patent_figures_cnt] => 13
[patent_no_of_words] => 17470
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 220
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17127502
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/127502 | One-ladder read of memory cells coarsely programmed via interleaved two-pass data programming techniques | Dec 17, 2020 | Issued |
Array
(
[id] => 16751518
[patent_doc_number] => 20210103527
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-04-08
[patent_title] => MEMORY DISABLEMENT FOR DATA SECURITY
[patent_app_type] => utility
[patent_app_number] => 17/124312
[patent_app_country] => US
[patent_app_date] => 2020-12-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 6334
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 78
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17124312
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/124312 | Memory disablement for data security | Dec 15, 2020 | Issued |
Array
(
[id] => 18967232
[patent_doc_number] => 11901010
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2024-02-13
[patent_title] => Enhanced gradient seeding scheme during a program operation in a memory sub-system
[patent_app_type] => utility
[patent_app_number] => 17/247576
[patent_app_country] => US
[patent_app_date] => 2020-12-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 11603
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 211
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17247576
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/247576 | Enhanced gradient seeding scheme during a program operation in a memory sub-system | Dec 15, 2020 | Issued |
Array
(
[id] => 16730918
[patent_doc_number] => 20210098066
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-04-01
[patent_title] => SEMICONDUCTOR MEMORY DEVICE AND METHOD OF OPERATING THE SAME
[patent_app_type] => utility
[patent_app_number] => 17/122485
[patent_app_country] => US
[patent_app_date] => 2020-12-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 14560
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -12
[patent_words_short_claim] => 72
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17122485
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/122485 | Semiconductor memory device and method of operating the same | Dec 14, 2020 | Issued |
Array
(
[id] => 17941470
[patent_doc_number] => 11475929
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2022-10-18
[patent_title] => Memory refresh
[patent_app_type] => utility
[patent_app_number] => 17/118843
[patent_app_country] => US
[patent_app_date] => 2020-12-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 8083
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 105
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17118843
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/118843 | Memory refresh | Dec 10, 2020 | Issued |
Array
(
[id] => 17878358
[patent_doc_number] => 11450379
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2022-09-20
[patent_title] => Ultra-compact page buffer
[patent_app_type] => utility
[patent_app_number] => 17/247437
[patent_app_country] => US
[patent_app_date] => 2020-12-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 13
[patent_no_of_words] => 9368
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 100
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17247437
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/247437 | Ultra-compact page buffer | Dec 9, 2020 | Issued |
Array
(
[id] => 18120368
[patent_doc_number] => 11551766
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2023-01-10
[patent_title] => Memory device and operating method thereof
[patent_app_type] => utility
[patent_app_number] => 16/950197
[patent_app_country] => US
[patent_app_date] => 2020-11-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 12
[patent_no_of_words] => 7919
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 120
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16950197
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/950197 | Memory device and operating method thereof | Nov 16, 2020 | Issued |
Array
(
[id] => 16811787
[patent_doc_number] => 20210134342
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-05-06
[patent_title] => SELF-REFERENCE SENSING FOR MEMORY CELLS
[patent_app_type] => utility
[patent_app_number] => 17/097749
[patent_app_country] => US
[patent_app_date] => 2020-11-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 11257
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17097749
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/097749 | Self-reference sensing for memory cells | Nov 12, 2020 | Issued |
Array
(
[id] => 18463370
[patent_doc_number] => 11687660
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2023-06-27
[patent_title] => Ephemeral peripheral device
[patent_app_type] => utility
[patent_app_number] => 17/096123
[patent_app_country] => US
[patent_app_date] => 2020-11-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 6
[patent_no_of_words] => 10746
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 227
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17096123
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/096123 | Ephemeral peripheral device | Nov 11, 2020 | Issued |
Array
(
[id] => 17599097
[patent_doc_number] => 20220148671
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-05-12
[patent_title] => SYSTEMS AND METHODS FOR READ ERROR RECOVERY
[patent_app_type] => utility
[patent_app_number] => 17/094218
[patent_app_country] => US
[patent_app_date] => 2020-11-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 10665
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 103
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17094218
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/094218 | Systems and methods for read error recovery | Nov 9, 2020 | Issued |
Array
(
[id] => 19137863
[patent_doc_number] => 11972834
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2024-04-30
[patent_title] => Low power and robust level-shifting pulse latch for dual-power memories
[patent_app_type] => utility
[patent_app_number] => 17/774138
[patent_app_country] => US
[patent_app_date] => 2020-11-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 4801
[patent_no_of_claims] => 25
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 99
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17774138
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/774138 | Low power and robust level-shifting pulse latch for dual-power memories | Nov 8, 2020 | Issued |
Array
(
[id] => 17224482
[patent_doc_number] => 11176992
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2021-11-16
[patent_title] => Memory write operation apparatus and method
[patent_app_type] => utility
[patent_app_number] => 17/086499
[patent_app_country] => US
[patent_app_date] => 2020-11-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 7
[patent_no_of_words] => 6711
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 267
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17086499
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/086499 | Memory write operation apparatus and method | Nov 1, 2020 | Issued |
Array
(
[id] => 16631862
[patent_doc_number] => 20210050516
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-02-18
[patent_title] => RESISTIVE MEMORY DEVICE HAVING A CONDUCTIVE BARRIER LAYER
[patent_app_type] => utility
[patent_app_number] => 17/074185
[patent_app_country] => US
[patent_app_date] => 2020-10-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 15109
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 194
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17074185
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/074185 | RESISTIVE MEMORY DEVICE HAVING A CONDUCTIVE BARRIER LAYER | Oct 18, 2020 | Abandoned |
Array
(
[id] => 18024030
[patent_doc_number] => 20220375529
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-11-24
[patent_title] => Memory Device, Operation Method of Memory Device, Data Processing Device, Data Processing System, and Electronic Device
[patent_app_type] => utility
[patent_app_number] => 17/772740
[patent_app_country] => US
[patent_app_date] => 2020-10-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 46696
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -11
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17772740
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/772740 | Memory device, operation method of memory device, data processing device, data processing system, and electronic device | Oct 15, 2020 | Issued |
Array
(
[id] => 17861508
[patent_doc_number] => 11442664
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2022-09-13
[patent_title] => Memory system and method of operating the same
[patent_app_type] => utility
[patent_app_number] => 17/069938
[patent_app_country] => US
[patent_app_date] => 2020-10-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 18
[patent_no_of_words] => 12315
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 114
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17069938
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/069938 | Memory system and method of operating the same | Oct 13, 2020 | Issued |
Array
(
[id] => 17499443
[patent_doc_number] => 11288149
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2022-03-29
[patent_title] => Flash memory block retirement policy
[patent_app_type] => utility
[patent_app_number] => 17/065254
[patent_app_country] => US
[patent_app_date] => 2020-10-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 13053
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 165
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17065254
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/065254 | Flash memory block retirement policy | Oct 6, 2020 | Issued |
Array
(
[id] => 17121010
[patent_doc_number] => 11132142
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2021-09-28
[patent_title] => Systems and methods for writing zeros to a memory array
[patent_app_type] => utility
[patent_app_number] => 17/063463
[patent_app_country] => US
[patent_app_date] => 2020-10-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 8
[patent_no_of_words] => 6672
[patent_no_of_claims] => 23
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 114
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17063463
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/063463 | Systems and methods for writing zeros to a memory array | Oct 4, 2020 | Issued |
Array
(
[id] => 16616959
[patent_doc_number] => 20210035612
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-02-04
[patent_title] => MEMORY ARRAY DECODING AND INTERCONNECTS
[patent_app_type] => utility
[patent_app_number] => 17/062024
[patent_app_country] => US
[patent_app_date] => 2020-10-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 44314
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 69
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17062024
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/062024 | Memory array decoding and interconnects | Oct 1, 2020 | Issued |
Array
(
[id] => 17493260
[patent_doc_number] => 11282570
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2022-03-22
[patent_title] => Storage device and method of operating the same
[patent_app_type] => utility
[patent_app_number] => 17/036853
[patent_app_country] => US
[patent_app_date] => 2020-09-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 13
[patent_no_of_words] => 10910
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 124
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17036853
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/036853 | Storage device and method of operating the same | Sep 28, 2020 | Issued |
Array
(
[id] => 17878357
[patent_doc_number] => 11450378
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2022-09-20
[patent_title] => Apparatuses and methods of power supply control for threshold voltage compensated sense amplifiers
[patent_app_type] => utility
[patent_app_number] => 17/037467
[patent_app_country] => US
[patent_app_date] => 2020-09-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 15
[patent_no_of_words] => 13797
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 91
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17037467
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/037467 | Apparatuses and methods of power supply control for threshold voltage compensated sense amplifiers | Sep 28, 2020 | Issued |