Search

Douglas King

Examiner (ID: 15404, Phone: (571)272-2311 , Office: P/2824 )

Most Active Art Unit
2824
Art Unit(s)
2824
Total Applications
1004
Issued Applications
774
Pending Applications
71
Abandoned Applications
171

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 16936092 [patent_doc_number] => 20210201981 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-07-01 [patent_title] => SEMICONDUCTOR DEVICE WITH WORD LINE DEGRADATION MONITOR AND ASSOCIATED METHODS AND SYSTEMS [patent_app_type] => utility [patent_app_number] => 17/022030 [patent_app_country] => US [patent_app_date] => 2020-09-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12877 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17022030 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/022030
Semiconductor device with word line degradation monitor and associated methods and systems Sep 14, 2020 Issued
Array ( [id] => 17092675 [patent_doc_number] => 11120869 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-09-14 [patent_title] => Quantizing loop memory cell system [patent_app_type] => utility [patent_app_number] => 17/021675 [patent_app_country] => US [patent_app_date] => 2020-09-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 13 [patent_no_of_words] => 10469 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 153 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17021675 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/021675
Quantizing loop memory cell system Sep 14, 2020 Issued
Array ( [id] => 18430317 [patent_doc_number] => 11675535 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-06-13 [patent_title] => Memory system and shift register memory [patent_app_type] => utility [patent_app_number] => 17/015893 [patent_app_country] => US [patent_app_date] => 2020-09-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 55 [patent_figures_cnt] => 57 [patent_no_of_words] => 25995 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 341 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17015893 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/015893
Memory system and shift register memory Sep 8, 2020 Issued
Array ( [id] => 16528511 [patent_doc_number] => 20200402592 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-12-24 [patent_title] => NON-VOLATILE MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 17/010100 [patent_app_country] => US [patent_app_date] => 2020-09-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13406 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17010100 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/010100
Non-volatile memory device Sep 1, 2020 Issued
Array ( [id] => 16515830 [patent_doc_number] => 20200395088 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-12-17 [patent_title] => MEMORY DEVICE AND MEMORY SYSTEM [patent_app_type] => utility [patent_app_number] => 17/008883 [patent_app_country] => US [patent_app_date] => 2020-09-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 18870 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17008883 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/008883
Memory device and memory system Aug 31, 2020 Issued
Array ( [id] => 16723535 [patent_doc_number] => 20210090682 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-03-25 [patent_title] => MEMORY SYSTEM [patent_app_type] => utility [patent_app_number] => 17/003937 [patent_app_country] => US [patent_app_date] => 2020-08-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 25637 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17003937 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/003937
Memory system Aug 25, 2020 Issued
Array ( [id] => 18174943 [patent_doc_number] => 11574660 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-02-07 [patent_title] => Circuits and methods for capacitor modulation [patent_app_type] => utility [patent_app_number] => 16/989883 [patent_app_country] => US [patent_app_date] => 2020-08-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5435 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 197 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16989883 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/989883
Circuits and methods for capacitor modulation Aug 10, 2020 Issued
Array ( [id] => 17787590 [patent_doc_number] => 11410724 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-08-09 [patent_title] => Semiconductor device and data reading method using the same [patent_app_type] => utility [patent_app_number] => 16/987618 [patent_app_country] => US [patent_app_date] => 2020-08-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 14238 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 228 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16987618 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/987618
Semiconductor device and data reading method using the same Aug 6, 2020 Issued
Array ( [id] => 18016131 [patent_doc_number] => 11508434 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-11-22 [patent_title] => Semiconductor memory device and method for operating the same [patent_app_type] => utility [patent_app_number] => 16/984743 [patent_app_country] => US [patent_app_date] => 2020-08-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 15 [patent_no_of_words] => 14562 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 231 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16984743 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/984743
Semiconductor memory device and method for operating the same Aug 3, 2020 Issued
Array ( [id] => 16440149 [patent_doc_number] => 20200357476 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-11-12 [patent_title] => NON-VOLATILE MEMORY DEVICE AND PROGRAMMING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 16/942148 [patent_app_country] => US [patent_app_date] => 2020-07-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14061 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 42 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16942148 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/942148
Non-volatile memory device and programming method thereof Jul 28, 2020 Issued
Array ( [id] => 17745445 [patent_doc_number] => 11393524 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-07-19 [patent_title] => Semiconductor memory and operating method thereof [patent_app_type] => utility [patent_app_number] => 16/941089 [patent_app_country] => US [patent_app_date] => 2020-07-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 15 [patent_no_of_words] => 8166 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 156 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16941089 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/941089
Semiconductor memory and operating method thereof Jul 27, 2020 Issued
Array ( [id] => 17210486 [patent_doc_number] => 11170861 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2021-11-09 [patent_title] => Non-volatile memory with multi-level cell array and associated program control method [patent_app_type] => utility [patent_app_number] => 16/939573 [patent_app_country] => US [patent_app_date] => 2020-07-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 18 [patent_no_of_words] => 8582 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 343 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16939573 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/939573
Non-volatile memory with multi-level cell array and associated program control method Jul 26, 2020 Issued
Array ( [id] => 16995168 [patent_doc_number] => 20210233588 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-07-29 [patent_title] => SEMICONDUCTOR MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 16/932190 [patent_app_country] => US [patent_app_date] => 2020-07-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11700 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16932190 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/932190
Semiconductor memory device Jul 16, 2020 Issued
Array ( [id] => 17345612 [patent_doc_number] => 20220011943 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-01-13 [patent_title] => METHODS AND DEVICES FOR WEAR LEVELING [patent_app_type] => utility [patent_app_number] => 16/925104 [patent_app_country] => US [patent_app_date] => 2020-07-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10820 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16925104 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/925104
Methods and devices for wear leveling Jul 8, 2020 Issued
Array ( [id] => 17492102 [patent_doc_number] => 11281405 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-03-22 [patent_title] => Controlled die asymmetry during MLC operations for optimal system pipeline [patent_app_type] => utility [patent_app_number] => 16/896029 [patent_app_country] => US [patent_app_date] => 2020-06-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 13 [patent_no_of_words] => 14068 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16896029 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/896029
Controlled die asymmetry during MLC operations for optimal system pipeline Jun 7, 2020 Issued
Array ( [id] => 19029757 [patent_doc_number] => 11929120 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-03-12 [patent_title] => Electronic memory devices [patent_app_type] => utility [patent_app_number] => 17/614813 [patent_app_country] => US [patent_app_date] => 2020-05-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 10422 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 291 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17614813 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/614813
Electronic memory devices May 27, 2020 Issued
Array ( [id] => 17707333 [patent_doc_number] => 20220207340 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-06-30 [patent_title] => SYNAPSE-MIMETIC DEVICE CAPABLE OF NEURAL NETWORK TRAINING [patent_app_type] => utility [patent_app_number] => 17/610027 [patent_app_country] => US [patent_app_date] => 2020-05-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4852 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -10 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17610027 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/610027
SYNAPSE-MIMETIC DEVICE CAPABLE OF NEURAL NETWORK TRAINING May 20, 2020 Pending
Array ( [id] => 17410017 [patent_doc_number] => 11250913 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-02-15 [patent_title] => Scrambling using different scrambling seeds for defect reduction and improved programming efficiency [patent_app_type] => utility [patent_app_number] => 16/880845 [patent_app_country] => US [patent_app_date] => 2020-05-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 8861 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16880845 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/880845
Scrambling using different scrambling seeds for defect reduction and improved programming efficiency May 20, 2020 Issued
Array ( [id] => 16286002 [patent_doc_number] => 20200279604 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-09-03 [patent_title] => DEDICATED READ VOLTAGES FOR DATA STRUCTURES [patent_app_type] => utility [patent_app_number] => 16/876641 [patent_app_country] => US [patent_app_date] => 2020-05-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8972 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16876641 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/876641
Dedicated read voltages for data structures May 17, 2020 Issued
Array ( [id] => 16470794 [patent_doc_number] => 20200372331 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-11-26 [patent_title] => CONTROL CIRCUIT FOR MULTIPLY ACCUMULATE CIRCUIT OF NEURAL NETWORK SYSTEM [patent_app_type] => utility [patent_app_number] => 16/874875 [patent_app_country] => US [patent_app_date] => 2020-05-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6729 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 168 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16874875 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/874875
Control circuit for multiply accumulate circuit of neural network system May 14, 2020 Issued
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