
Douglas King
Examiner (ID: 15404, Phone: (571)272-2311 , Office: P/2824 )
| Most Active Art Unit | 2824 |
| Art Unit(s) | 2824 |
| Total Applications | 1004 |
| Issued Applications | 774 |
| Pending Applications | 71 |
| Abandoned Applications | 171 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 18052897
[patent_doc_number] => 11526279
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2022-12-13
[patent_title] => Technologies for performing column architecture-aware scrambling
[patent_app_type] => utility
[patent_app_number] => 15/930035
[patent_app_country] => US
[patent_app_date] => 2020-05-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 8
[patent_no_of_words] => 6533
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 196
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15930035
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/930035 | Technologies for performing column architecture-aware scrambling | May 11, 2020 | Issued |
Array
(
[id] => 17424085
[patent_doc_number] => 11257546
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2022-02-22
[patent_title] => Reading of soft bits and hard bits from memory cells
[patent_app_type] => utility
[patent_app_number] => 16/869488
[patent_app_country] => US
[patent_app_date] => 2020-05-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 11818
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 164
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16869488
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/869488 | Reading of soft bits and hard bits from memory cells | May 6, 2020 | Issued |
Array
(
[id] => 16424802
[patent_doc_number] => 20200350000
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-11-05
[patent_title] => EFUSE MEMORY CELL AND EFUSE MEMORY, AND WRITE/READ METHODS THEREOF
[patent_app_type] => utility
[patent_app_number] => 16/864490
[patent_app_country] => US
[patent_app_date] => 2020-05-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 4664
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -5
[patent_words_short_claim] => 184
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16864490
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/864490 | EFUSE MEMORY CELL AND EFUSE MEMORY, AND WRITE/READ METHODS THEREOF | Apr 30, 2020 | Abandoned |
Array
(
[id] => 17173819
[patent_doc_number] => 20210327490
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-10-21
[patent_title] => APPARATUSES AND METHODS FOR PROVIDING MAIN WORD LINE SIGNAL WITH DYNAMIC WELL
[patent_app_type] => utility
[patent_app_number] => 16/853417
[patent_app_country] => US
[patent_app_date] => 2020-04-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 9195
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 58
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16853417
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/853417 | Apparatuses and methods for providing main word line signal with dynamic well | Apr 19, 2020 | Issued |
Array
(
[id] => 16455121
[patent_doc_number] => 20200364547
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-11-19
[patent_title] => CHIP INCLUDING NEURAL NETWORK PROCESSORS AND METHODS FOR MANUFACTURING THE SAME
[patent_app_type] => utility
[patent_app_number] => 16/852241
[patent_app_country] => US
[patent_app_date] => 2020-04-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 4638
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -11
[patent_words_short_claim] => 55
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16852241
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/852241 | CHIP INCLUDING NEURAL NETWORK PROCESSORS AND METHODS FOR MANUFACTURING THE SAME | Apr 16, 2020 | Pending |
Array
(
[id] => 16684154
[patent_doc_number] => 10943643
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2021-03-09
[patent_title] => Semiconductor storage circuit
[patent_app_type] => utility
[patent_app_number] => 16/847551
[patent_app_country] => US
[patent_app_date] => 2020-04-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 10
[patent_no_of_words] => 4518
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 215
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16847551
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/847551 | Semiconductor storage circuit | Apr 12, 2020 | Issued |
Array
(
[id] => 18401320
[patent_doc_number] => 11663458
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2023-05-30
[patent_title] => Conductance drift corrections in neuromorphic systems based on crossbar array structures
[patent_app_type] => utility
[patent_app_number] => 16/842874
[patent_app_country] => US
[patent_app_date] => 2020-04-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 5
[patent_no_of_words] => 8166
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 218
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16842874
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/842874 | Conductance drift corrections in neuromorphic systems based on crossbar array structures | Apr 7, 2020 | Issued |
Array
(
[id] => 17925700
[patent_doc_number] => 11468960
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2022-10-11
[patent_title] => Semiconductor device with selective command delay and associated methods and systems
[patent_app_type] => utility
[patent_app_number] => 16/839371
[patent_app_country] => US
[patent_app_date] => 2020-04-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 11467
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 86
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16839371
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/839371 | Semiconductor device with selective command delay and associated methods and systems | Apr 2, 2020 | Issued |
Array
(
[id] => 16958882
[patent_doc_number] => 11062759
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2021-07-13
[patent_title] => Memory device and programming method thereof
[patent_app_type] => utility
[patent_app_number] => 16/837041
[patent_app_country] => US
[patent_app_date] => 2020-04-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 15
[patent_no_of_words] => 5914
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 335
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16837041
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/837041 | Memory device and programming method thereof | Mar 31, 2020 | Issued |
Array
(
[id] => 16315819
[patent_doc_number] => 20200294557
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-09-17
[patent_title] => LOW POWER SIGNALING INTERFACE
[patent_app_type] => utility
[patent_app_number] => 16/828591
[patent_app_country] => US
[patent_app_date] => 2020-03-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 11241
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16828591
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/828591 | Synchronous signaling interface with over-clocked timing reference | Mar 23, 2020 | Issued |
Array
(
[id] => 17195879
[patent_doc_number] => 11164644
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2021-11-02
[patent_title] => Storage device and method of operating the same
[patent_app_type] => utility
[patent_app_number] => 16/827358
[patent_app_country] => US
[patent_app_date] => 2020-03-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 12
[patent_no_of_words] => 10333
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 89
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16827358
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/827358 | Storage device and method of operating the same | Mar 22, 2020 | Issued |
Array
(
[id] => 16162695
[patent_doc_number] => 20200219580
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-07-09
[patent_title] => ERROR CORRECTION FOR DYNAMIC DATA IN A MEMORY THAT IS ROW ADDRESSABLE AND COLUMN ADDRESSABLE
[patent_app_type] => utility
[patent_app_number] => 16/827235
[patent_app_country] => US
[patent_app_date] => 2020-03-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 19646
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 121
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16827235
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/827235 | Error correction for dynamic data in a memory that is row addressable and column addressable | Mar 22, 2020 | Issued |
Array
(
[id] => 16347769
[patent_doc_number] => 20200312420
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-10-01
[patent_title] => ERROR REMAPPING
[patent_app_type] => utility
[patent_app_number] => 16/823908
[patent_app_country] => US
[patent_app_date] => 2020-03-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 3896
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 60
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16823908
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/823908 | Error remapping | Mar 18, 2020 | Issued |
Array
(
[id] => 17165971
[patent_doc_number] => 11152079
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2021-10-19
[patent_title] => Circuits and methods for reliable replacement of bad columns in a memory device
[patent_app_type] => utility
[patent_app_number] => 16/824362
[patent_app_country] => US
[patent_app_date] => 2020-03-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 19
[patent_figures_cnt] => 29
[patent_no_of_words] => 17613
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 67
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16824362
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/824362 | Circuits and methods for reliable replacement of bad columns in a memory device | Mar 18, 2020 | Issued |
Array
(
[id] => 17115331
[patent_doc_number] => 20210295928
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-09-23
[patent_title] => ADJUSTING READ VOLTAGE LEVELS BASED ON A PROGRAMMED BIT COUNT IN A MEMORY SUB-SYSTEM
[patent_app_type] => utility
[patent_app_number] => 16/822561
[patent_app_country] => US
[patent_app_date] => 2020-03-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 6478
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 83
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16822561
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/822561 | Adjusting read voltage levels based on a programmed bit count in a memory sub-system | Mar 17, 2020 | Issued |
Array
(
[id] => 16332066
[patent_doc_number] => 20200303032
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-09-24
[patent_title] => TEST DEVICE AND TEST METHOD OF SEMICONDUCTOR STORAGE DEVICE
[patent_app_type] => utility
[patent_app_number] => 16/813743
[patent_app_country] => US
[patent_app_date] => 2020-03-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 5139
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -6
[patent_words_short_claim] => 265
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16813743
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/813743 | Test device and test method of semiconductor storage device | Mar 9, 2020 | Issued |
Array
(
[id] => 16668266
[patent_doc_number] => 10937519
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2021-03-02
[patent_title] => Memory devices, memory systems and methods of operating memory devices
[patent_app_type] => utility
[patent_app_number] => 16/813889
[patent_app_country] => US
[patent_app_date] => 2020-03-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 20
[patent_figures_cnt] => 27
[patent_no_of_words] => 11808
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 253
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16813889
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/813889 | Memory devices, memory systems and methods of operating memory devices | Mar 9, 2020 | Issued |
Array
(
[id] => 16715370
[patent_doc_number] => 20210082517
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-03-18
[patent_title] => Non-volatile Memory Device With Stored Index Information
[patent_app_type] => utility
[patent_app_number] => 16/813317
[patent_app_country] => US
[patent_app_date] => 2020-03-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 4789
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -19
[patent_words_short_claim] => 130
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16813317
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/813317 | Non-volatile memory device with stored index information | Mar 8, 2020 | Issued |
Array
(
[id] => 16738716
[patent_doc_number] => 10964377
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2021-03-30
[patent_title] => Semiconductor storage device
[patent_app_type] => utility
[patent_app_number] => 16/807078
[patent_app_country] => US
[patent_app_date] => 2020-03-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 15
[patent_figures_cnt] => 19
[patent_no_of_words] => 11198
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 174
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16807078
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/807078 | Semiconductor storage device | Mar 1, 2020 | Issued |
Array
(
[id] => 17107232
[patent_doc_number] => 11127457
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2021-09-21
[patent_title] => Memory device with reduced read disturbance and method of operating the memory device
[patent_app_type] => utility
[patent_app_number] => 16/803450
[patent_app_country] => US
[patent_app_date] => 2020-02-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 20
[patent_figures_cnt] => 26
[patent_no_of_words] => 13899
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 160
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16803450
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/803450 | Memory device with reduced read disturbance and method of operating the memory device | Feb 26, 2020 | Issued |