Search

Douglas King

Examiner (ID: 15404, Phone: (571)272-2311 , Office: P/2824 )

Most Active Art Unit
2824
Art Unit(s)
2824
Total Applications
1004
Issued Applications
774
Pending Applications
71
Abandoned Applications
171

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 16234001 [patent_doc_number] => 10741565 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-08-11 [patent_title] => 3D SRAM circuit with double gate transistors with improved layout [patent_app_type] => utility [patent_app_number] => 16/379476 [patent_app_country] => US [patent_app_date] => 2019-04-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 17 [patent_no_of_words] => 6289 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 176 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16379476 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/379476
3D SRAM circuit with double gate transistors with improved layout Apr 8, 2019 Issued
Array ( [id] => 16819670 [patent_doc_number] => 11004507 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-05-11 [patent_title] => Methods and systems for detecting degradation of resistive memory devices [patent_app_type] => utility [patent_app_number] => 16/377420 [patent_app_country] => US [patent_app_date] => 2019-04-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 27 [patent_no_of_words] => 13014 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 227 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16377420 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/377420
Methods and systems for detecting degradation of resistive memory devices Apr 7, 2019 Issued
Array ( [id] => 16347737 [patent_doc_number] => 20200312388 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-10-01 [patent_title] => CENTRALIZED PLACEMENT OF COMMAND AND ADDRESS SWAPPING IN MEMORY DEVICES [patent_app_type] => utility [patent_app_number] => 16/365218 [patent_app_country] => US [patent_app_date] => 2019-03-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6975 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 202 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16365218 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/365218
Centralized placement of command and address swapping in memory devices Mar 25, 2019 Issued
Array ( [id] => 16256539 [patent_doc_number] => 20200265914 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-08-20 [patent_title] => MEMORY STORAGE APPARATUS AND FORMING METHOD OF RESISTIVE MEMORY DEVICE THEREOF [patent_app_type] => utility [patent_app_number] => 16/281063 [patent_app_country] => US [patent_app_date] => 2019-02-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3149 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -11 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16281063 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/281063
Memory storage apparatus and forming method of resistive memory device thereof Feb 19, 2019 Issued
Array ( [id] => 16574811 [patent_doc_number] => 10896736 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-01-19 [patent_title] => Semiconductor memory device and NAND-type flash memory erase method [patent_app_type] => utility [patent_app_number] => 16/279167 [patent_app_country] => US [patent_app_date] => 2019-02-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 12 [patent_no_of_words] => 4728 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16279167 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/279167
Semiconductor memory device and NAND-type flash memory erase method Feb 18, 2019 Issued
Array ( [id] => 16536245 [patent_doc_number] => 10878858 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-12-29 [patent_title] => Apparatuses including input buffers and methods for operating input buffers [patent_app_type] => utility [patent_app_number] => 16/276481 [patent_app_country] => US [patent_app_date] => 2019-02-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 8583 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16276481 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/276481
Apparatuses including input buffers and methods for operating input buffers Feb 13, 2019 Issued
Array ( [id] => 15369219 [patent_doc_number] => 20200020374 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-01-16 [patent_title] => MAGNETIC MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 16/273387 [patent_app_country] => US [patent_app_date] => 2019-02-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 19059 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 276 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16273387 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/273387
Magnetic memory device Feb 11, 2019 Issued
Array ( [id] => 19213428 [patent_doc_number] => 12002500 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-06-04 [patent_title] => Writing method and erasing method of fusion memory [patent_app_type] => utility [patent_app_number] => 17/426053 [patent_app_country] => US [patent_app_date] => 2019-01-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 20 [patent_no_of_words] => 8134 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 287 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17426053 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/426053
Writing method and erasing method of fusion memory Jan 27, 2019 Issued
Array ( [id] => 17667516 [patent_doc_number] => 11361216 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-06-14 [patent_title] => Neural network circuits having non-volatile synapse arrays [patent_app_type] => utility [patent_app_number] => 16/252640 [patent_app_country] => US [patent_app_date] => 2019-01-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 31 [patent_no_of_words] => 11561 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 373 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16252640 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/252640
Neural network circuits having non-volatile synapse arrays Jan 19, 2019 Issued
Array ( [id] => 16700050 [patent_doc_number] => 10950658 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-03-16 [patent_title] => Circuit and method to enhance efficiency of memory [patent_app_type] => utility [patent_app_number] => 16/245857 [patent_app_country] => US [patent_app_date] => 2019-01-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6321 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 201 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16245857 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/245857
Circuit and method to enhance efficiency of memory Jan 10, 2019 Issued
Array ( [id] => 16432676 [patent_doc_number] => 10832769 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-11-10 [patent_title] => Memory device with a charge transfer device [patent_app_type] => utility [patent_app_number] => 16/232347 [patent_app_country] => US [patent_app_date] => 2018-12-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 25658 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16232347 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/232347
Memory device with a charge transfer device Dec 25, 2018 Issued
Array ( [id] => 14603051 [patent_doc_number] => 10354719 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-07-16 [patent_title] => 3D structure for advanced SRAM design to avoid half-selected issue [patent_app_type] => utility [patent_app_number] => 16/226956 [patent_app_country] => US [patent_app_date] => 2018-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 4278 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 168 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16226956 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/226956
3D structure for advanced SRAM design to avoid half-selected issue Dec 19, 2018 Issued
Array ( [id] => 17002348 [patent_doc_number] => 11081170 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-08-03 [patent_title] => Apparatus and methods for programming memory cells responsive to an indication of age of the memory cells [patent_app_type] => utility [patent_app_number] => 16/225036 [patent_app_country] => US [patent_app_date] => 2018-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 19 [patent_no_of_words] => 11516 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 379 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16225036 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/225036
Apparatus and methods for programming memory cells responsive to an indication of age of the memory cells Dec 18, 2018 Issued
Array ( [id] => 14572951 [patent_doc_number] => 20190214083 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-07-11 [patent_title] => Method of Real-Time Access to a Differential Memory, Differential Memory and Electronic System [patent_app_type] => utility [patent_app_number] => 16/225492 [patent_app_country] => US [patent_app_date] => 2018-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5504 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16225492 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/225492
Method of real-time access to a differential memory, differential memory and electronic system Dec 18, 2018 Issued
Array ( [id] => 16409763 [patent_doc_number] => 10818324 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-10-27 [patent_title] => Memory array decoding and interconnects [patent_app_type] => utility [patent_app_number] => 16/223632 [patent_app_country] => US [patent_app_date] => 2018-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 47 [patent_figures_cnt] => 89 [patent_no_of_words] => 44268 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 64 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16223632 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/223632
Memory array decoding and interconnects Dec 17, 2018 Issued
Array ( [id] => 16788963 [patent_doc_number] => 10991400 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-04-27 [patent_title] => Integrated circuit [patent_app_type] => utility [patent_app_number] => 16/221757 [patent_app_country] => US [patent_app_date] => 2018-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4277 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16221757 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/221757
Integrated circuit Dec 16, 2018 Issued
Array ( [id] => 16285996 [patent_doc_number] => 20200279598 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-09-03 [patent_title] => THREE-DIMENSIONAL NON-VOLATILE FERROELECTRIC MEMORY [patent_app_type] => utility [patent_app_number] => 16/760581 [patent_app_country] => US [patent_app_date] => 2018-12-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16344 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 198 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16760581 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/760581
Three-dimensional non-volatile ferroelectric memory Dec 9, 2018 Issued
Array ( [id] => 15998155 [patent_doc_number] => 20200174948 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-06-04 [patent_title] => MEMORY DISABLEMENT FOR DATA SECURITY [patent_app_type] => utility [patent_app_number] => 16/204656 [patent_app_country] => US [patent_app_date] => 2018-11-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6308 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -22 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16204656 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/204656
Memory disablement for data security Nov 28, 2018 Issued
Array ( [id] => 14381415 [patent_doc_number] => 20190164620 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-05-30 [patent_title] => Electronic Device [patent_app_type] => utility [patent_app_number] => 16/199603 [patent_app_country] => US [patent_app_date] => 2018-11-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 19866 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16199603 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/199603
Electronic device Nov 25, 2018 Issued
Array ( [id] => 17667515 [patent_doc_number] => 11361215 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-06-14 [patent_title] => Neural network circuits having non-volatile synapse arrays [patent_app_type] => utility [patent_app_number] => 16/196617 [patent_app_country] => US [patent_app_date] => 2018-11-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 18 [patent_no_of_words] => 8855 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 196 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16196617 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/196617
Neural network circuits having non-volatile synapse arrays Nov 19, 2018 Issued
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