Search

Douglas King

Examiner (ID: 15404, Phone: (571)272-2311 , Office: P/2824 )

Most Active Art Unit
2824
Art Unit(s)
2824
Total Applications
1004
Issued Applications
774
Pending Applications
71
Abandoned Applications
171

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 13799039 [patent_doc_number] => 20190013058 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-01-10 [patent_title] => SELF-REFERENCE SENSING FOR MEMORY CELLS [patent_app_type] => utility [patent_app_number] => 15/641783 [patent_app_country] => US [patent_app_date] => 2017-07-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11160 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -20 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15641783 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/641783
Self-reference sensing for memory cells Jul 4, 2017 Issued
Array ( [id] => 12005189 [patent_doc_number] => 20170309344 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-10-26 [patent_title] => 'MULTI-DIE PROGRAMMING WITH DIE-JUMPING INDUCED PERIODIC DELAYS' [patent_app_type] => utility [patent_app_number] => 15/640563 [patent_app_country] => US [patent_app_date] => 2017-07-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 12756 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15640563 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/640563
Multi-die programming with die-jumping induced periodic delays Jul 1, 2017 Issued
Array ( [id] => 13784955 [patent_doc_number] => 20190006016 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-01-03 [patent_title] => METHOD, SYSTEM, AND APPARATUS FOR DETECTING FAILURE OF PROGRAMMING OF A MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 15/638260 [patent_app_country] => US [patent_app_date] => 2017-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6686 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15638260 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/638260
METHOD, SYSTEM, AND APPARATUS FOR DETECTING FAILURE OF PROGRAMMING OF A MEMORY DEVICE Jun 28, 2017 Abandoned
Array ( [id] => 13540653 [patent_doc_number] => 20180321873 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-11-08 [patent_title] => MEMORY SYSTEM AND OPERATING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 15/587641 [patent_app_country] => US [patent_app_date] => 2017-05-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4042 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -20 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15587641 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/587641
Memory system and operating method thereof May 4, 2017 Issued
Array ( [id] => 16593640 [patent_doc_number] => 10902916 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-01-26 [patent_title] => Semiconductor circuit, driving method, and electronic apparatus [patent_app_type] => utility [patent_app_number] => 16/099251 [patent_app_country] => US [patent_app_date] => 2017-04-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 32 [patent_figures_cnt] => 47 [patent_no_of_words] => 22912 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 298 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16099251 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/099251
Semiconductor circuit, driving method, and electronic apparatus Apr 19, 2017 Issued
Array ( [id] => 15014733 [patent_doc_number] => 10453522 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-10-22 [patent_title] => SRAM with stacked bit cells [patent_app_type] => utility [patent_app_number] => 15/487526 [patent_app_country] => US [patent_app_date] => 2017-04-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 8060 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 236 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15487526 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/487526
SRAM with stacked bit cells Apr 13, 2017 Issued
Array ( [id] => 12614691 [patent_doc_number] => 20180096727 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-04-05 [patent_title] => Address Decoder for a Non-Volatile Memory Array Using MOS Selection Transistors [patent_app_type] => utility [patent_app_number] => 15/474607 [patent_app_country] => US [patent_app_date] => 2017-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5024 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 146 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15474607 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/474607
Address decoder for a non-volatile memory array using MOS selection transistors Mar 29, 2017 Issued
Array ( [id] => 11959157 [patent_doc_number] => 20170263308 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-09-14 [patent_title] => 'SRAM MEMORY BIT CELL COMPRISING N-TFET AND P-TFET' [patent_app_type] => utility [patent_app_number] => 15/452783 [patent_app_country] => US [patent_app_date] => 2017-03-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 8277 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15452783 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/452783
SRAM memory bit cell comprising n-TFET and p-TFET Mar 7, 2017 Issued
Array ( [id] => 12243052 [patent_doc_number] => 20180075915 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-03-15 [patent_title] => 'HIGH VOLTAGE SWITCH CIRCUIT AND SEMICONDUCTOR MEMORY DEVICE INCLUDING THE SAME' [patent_app_type] => utility [patent_app_number] => 15/453367 [patent_app_country] => US [patent_app_date] => 2017-03-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6914 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15453367 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/453367
High voltage switch circuit and semiconductor memory device including the same Mar 7, 2017 Issued
Array ( [id] => 12026734 [patent_doc_number] => 20170316833 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-11-02 [patent_title] => 'SENSE AMPLIFIER AND MEMORY DEVICE USING THE SAME' [patent_app_type] => utility [patent_app_number] => 15/452885 [patent_app_country] => US [patent_app_date] => 2017-03-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 8567 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15452885 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/452885
Sense amplifier and memory device using the same Mar 7, 2017 Issued
Array ( [id] => 13242543 [patent_doc_number] => 10134478 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-11-20 [patent_title] => Apparatuses and methods for reducing read disturb [patent_app_type] => utility [patent_app_number] => 15/436289 [patent_app_country] => US [patent_app_date] => 2017-02-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 4616 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15436289 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/436289
Apparatuses and methods for reducing read disturb Feb 16, 2017 Issued
Array ( [id] => 17099954 [patent_doc_number] => 20210287745 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-09-16 [patent_title] => CONVOLUTION OPERATION METHOD BASED ON NOR FLASH ARRAY [patent_app_type] => utility [patent_app_number] => 16/326946 [patent_app_country] => US [patent_app_date] => 2017-01-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4488 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -10 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16326946 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/326946
Convolution operation method based on NOR flash array Jan 24, 2017 Issued
Array ( [id] => 11592633 [patent_doc_number] => 20170117045 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-04-27 [patent_title] => 'ELECTRONIC DEVICE' [patent_app_type] => utility [patent_app_number] => 15/402109 [patent_app_country] => US [patent_app_date] => 2017-01-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 20351 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15402109 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/402109
Electronic device having semiconductor storage cells Jan 8, 2017 Issued
Array ( [id] => 11532391 [patent_doc_number] => 20170092369 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-03-30 [patent_title] => 'NONVOLATILE MEMORY DEVICE AND OPERATING METHOD THEREOF' [patent_app_type] => utility [patent_app_number] => 15/377504 [patent_app_country] => US [patent_app_date] => 2016-12-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 8477 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15377504 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/377504
Nonvolatile memory device and operating method thereof Dec 12, 2016 Issued
Array ( [id] => 15759811 [patent_doc_number] => 10622032 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-04-14 [patent_title] => Low power signaling interface [patent_app_type] => utility [patent_app_number] => 15/779977 [patent_app_country] => US [patent_app_date] => 2016-12-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 29 [patent_no_of_words] => 11241 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15779977 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/779977
Low power signaling interface Nov 30, 2016 Issued
Array ( [id] => 11622912 [patent_doc_number] => 20170133099 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-05-11 [patent_title] => '3D NAND ARRAY WITH DIVIDED STRING ARCHITECTURE' [patent_app_type] => utility [patent_app_number] => 15/348869 [patent_app_country] => US [patent_app_date] => 2016-11-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 5429 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15348869 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/348869
3D NAND ARRAY WITH DIVIDED STRING ARCHITECTURE Nov 9, 2016 Abandoned
Array ( [id] => 11578465 [patent_doc_number] => 09633734 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2017-04-25 [patent_title] => 'Driving circuit for non-volatile memory' [patent_app_type] => utility [patent_app_number] => 15/348369 [patent_app_country] => US [patent_app_date] => 2016-11-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 9 [patent_no_of_words] => 5925 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 678 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15348369 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/348369
Driving circuit for non-volatile memory Nov 9, 2016 Issued
Array ( [id] => 12712858 [patent_doc_number] => 20180129452 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-05-10 [patent_title] => METHOD AND SYSTEM OF ENHANCED RELIABILITY AND ERROR IMMUNITY IN FLASH STORAGE [patent_app_type] => utility [patent_app_number] => 15/343546 [patent_app_country] => US [patent_app_date] => 2016-11-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9289 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15343546 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/343546
Method and system of enhanced reliability and error immunity in flash storage Nov 3, 2016 Issued
Array ( [id] => 14394915 [patent_doc_number] => 10310741 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-06-04 [patent_title] => Nonvolatile memory device, data storage device and operating method thereof [patent_app_type] => utility [patent_app_number] => 15/337741 [patent_app_country] => US [patent_app_date] => 2016-10-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 5159 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 220 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15337741 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/337741
Nonvolatile memory device, data storage device and operating method thereof Oct 27, 2016 Issued
Array ( [id] => 11630637 [patent_doc_number] => 20170140825 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-05-18 [patent_title] => 'SOLID STATE DRIVE DEVICES AND STORAGE SYSTEMS HAVING THE SAME' [patent_app_type] => utility [patent_app_number] => 15/333384 [patent_app_country] => US [patent_app_date] => 2016-10-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 14137 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15333384 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/333384
Solid state drive devices and storage systems having the same Oct 24, 2016 Issued
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