Search

Douglas King

Examiner (ID: 15404, Phone: (571)272-2311 , Office: P/2824 )

Most Active Art Unit
2824
Art Unit(s)
2824
Total Applications
1004
Issued Applications
774
Pending Applications
71
Abandoned Applications
171

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 11055622 [patent_doc_number] => 20160252583 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-09-01 [patent_title] => 'APPARATUS FOR ESTIMATING STATE OF HYBRID SECONDARY BATTERY AND METHOD THEREOF' [patent_app_type] => utility [patent_app_number] => 15/028974 [patent_app_country] => US [patent_app_date] => 2014-10-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 13305 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15028974 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/028974
Apparatus for estimating state of hybrid secondary battery and method thereof Oct 13, 2014 Issued
Array ( [id] => 11062051 [patent_doc_number] => 20160259011 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-09-08 [patent_title] => 'APPARATUS FOR ESTIMATING STATE OF SECONDARY BATTERY INCLUDING BLENDED POSITIVE ELECTRODE MATERIAL AND METHOD THEREOF' [patent_app_type] => utility [patent_app_number] => 15/029048 [patent_app_country] => US [patent_app_date] => 2014-10-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 25 [patent_no_of_words] => 25562 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15029048 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/029048
Apparatus for estimating state of secondary battery including blended positive electrode material and method thereof Oct 13, 2014 Issued
Array ( [id] => 10752918 [patent_doc_number] => 20160099070 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-04-07 [patent_title] => 'Sensing Multiple Reference Levels In Non-Volatile Storage Elements' [patent_app_type] => utility [patent_app_number] => 14/508615 [patent_app_country] => US [patent_app_date] => 2014-10-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 26 [patent_no_of_words] => 18003 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14508615 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/508615
Sensing multiple reference levels in non-volatile storage elements Oct 6, 2014 Issued
Array ( [id] => 10752881 [patent_doc_number] => 20160099033 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-04-07 [patent_title] => 'COLUMN DECODER CIRCUITRY FOR A NON-VOLATILE MEMORY' [patent_app_type] => utility [patent_app_number] => 14/506865 [patent_app_country] => US [patent_app_date] => 2014-10-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 4847 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14506865 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/506865
COLUMN DECODER CIRCUITRY FOR A NON-VOLATILE MEMORY Oct 5, 2014 Abandoned
Array ( [id] => 15663539 [patent_doc_number] => 10595972 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-03-24 [patent_title] => Method and user interface for use in manufacturing multi-shaded dental restorations [patent_app_type] => utility [patent_app_number] => 15/027815 [patent_app_country] => US [patent_app_date] => 2014-10-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 24 [patent_no_of_words] => 12528 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 258 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15027815 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/027815
Method and user interface for use in manufacturing multi-shaded dental restorations Oct 1, 2014 Issued
Array ( [id] => 10425902 [patent_doc_number] => 20150310913 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-10-29 [patent_title] => 'ELECTRONIC DEVICE' [patent_app_type] => utility [patent_app_number] => 14/503069 [patent_app_country] => US [patent_app_date] => 2014-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 20352 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14503069 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/503069
Electronic device having semiconductor storage cells Sep 29, 2014 Issued
Array ( [id] => 12019490 [patent_doc_number] => 09812199 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-11-07 [patent_title] => 'Electronic device with semiconductor memory having variable resistance elements for storing data and associated driving circuitry' [patent_app_type] => utility [patent_app_number] => 14/503100 [patent_app_country] => US [patent_app_date] => 2014-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 16 [patent_no_of_words] => 19317 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 413 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14503100 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/503100
Electronic device with semiconductor memory having variable resistance elements for storing data and associated driving circuitry Sep 29, 2014 Issued
Array ( [id] => 10417898 [patent_doc_number] => 20150302908 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-10-22 [patent_title] => 'WRITE/READ PRIORITY BLOCKING SCHEME USING PARALLEL STATIC ADDRESS DECODE PATH' [patent_app_type] => utility [patent_app_number] => 14/501078 [patent_app_country] => US [patent_app_date] => 2014-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3067 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14501078 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/501078
Write/read priority blocking scheme using parallel static address decode path Sep 29, 2014 Issued
Array ( [id] => 10409693 [patent_doc_number] => 20150294702 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-10-15 [patent_title] => 'ELECTRONIC DEVICE' [patent_app_type] => utility [patent_app_number] => 14/501959 [patent_app_country] => US [patent_app_date] => 2014-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 19040 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14501959 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/501959
Electronic device having semiconductor memory comprising variable resistance elements for storing data Sep 29, 2014 Issued
Array ( [id] => 10463618 [patent_doc_number] => 20150348634 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-12-03 [patent_title] => 'SEMICONDUCTOR MEMORY DEVICE, MEMORY SYSTEM INCLUDING THE SAME, AND OPERATING METHOD THEREOF' [patent_app_type] => utility [patent_app_number] => 14/486361 [patent_app_country] => US [patent_app_date] => 2014-09-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5413 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14486361 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/486361
SEMICONDUCTOR MEMORY DEVICE, MEMORY SYSTEM INCLUDING THE SAME, AND OPERATING METHOD THEREOF Sep 14, 2014 Abandoned
Array ( [id] => 11876223 [patent_doc_number] => 09748003 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-08-29 [patent_title] => 'Efficient coding for memory redundancy' [patent_app_type] => utility [patent_app_number] => 14/485379 [patent_app_country] => US [patent_app_date] => 2014-09-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 5259 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 186 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14485379 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/485379
Efficient coding for memory redundancy Sep 11, 2014 Issued
Array ( [id] => 10409695 [patent_doc_number] => 20150294704 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-10-15 [patent_title] => 'ELECTRONIC DEVICE' [patent_app_type] => utility [patent_app_number] => 14/484236 [patent_app_country] => US [patent_app_date] => 2014-09-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 16834 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14484236 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/484236
ELECTRONIC DEVICE Sep 10, 2014 Abandoned
Array ( [id] => 10003864 [patent_doc_number] => 09047961 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-06-02 [patent_title] => 'Method of operating semiconductor device' [patent_app_type] => utility [patent_app_number] => 14/472620 [patent_app_country] => US [patent_app_date] => 2014-08-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 15 [patent_no_of_words] => 21112 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14472620 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/472620
Method of operating semiconductor device Aug 28, 2014 Issued
Array ( [id] => 10321586 [patent_doc_number] => 20150206590 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-07-23 [patent_title] => 'MEMORY SYSTEM' [patent_app_type] => utility [patent_app_number] => 14/463835 [patent_app_country] => US [patent_app_date] => 2014-08-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 11125 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14463835 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/463835
MEMORY SYSTEM Aug 19, 2014 Abandoned
Array ( [id] => 10944910 [patent_doc_number] => 20140347932 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-11-27 [patent_title] => 'MEMORY WITH THREE TRANSISTOR MEMORY CELL DEVICE' [patent_app_type] => utility [patent_app_number] => 14/455449 [patent_app_country] => US [patent_app_date] => 2014-08-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3812 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14455449 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/455449
Memory with three transistor memory cell device Aug 7, 2014 Issued
Array ( [id] => 10931201 [patent_doc_number] => 20140334223 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-11-13 [patent_title] => 'APPARATUSES AND METHODS FOR DETERMINING STABILITY OF A MEMORY CELL' [patent_app_type] => utility [patent_app_number] => 14/337989 [patent_app_country] => US [patent_app_date] => 2014-07-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6087 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14337989 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/337989
Apparatuses and methods for determining stability of a memory cell Jul 21, 2014 Issued
Array ( [id] => 10925112 [patent_doc_number] => 20140328134 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-11-06 [patent_title] => 'Sense Amplifiers, Memories, and Apparatuses and Methods for Sensing a Data State of a Memory Cell' [patent_app_type] => utility [patent_app_number] => 14/333164 [patent_app_country] => US [patent_app_date] => 2014-07-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4393 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14333164 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/333164
Sense amplifiers, memories, and apparatuses and methods for sensing a data state of a memory cell Jul 15, 2014 Issued
Array ( [id] => 10343321 [patent_doc_number] => 20150228326 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-08-13 [patent_title] => 'INTERNAL VOLTAGE GENERATION CIRCUIT, SEMICONDUCTOR MEMORY DEVICE AND SEMICONDUCTOR MEMORY SYSTEM' [patent_app_type] => utility [patent_app_number] => 14/326123 [patent_app_country] => US [patent_app_date] => 2014-07-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3847 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14326123 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/326123
Internal voltage generation circuit, semiconductor memory device and semiconductor memory system Jul 7, 2014 Issued
Array ( [id] => 10189446 [patent_doc_number] => 09218872 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2015-12-22 [patent_title] => 'Memory chip and layout design for manufacturing same' [patent_app_type] => utility [patent_app_number] => 14/310399 [patent_app_country] => US [patent_app_date] => 2014-06-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 20 [patent_no_of_words] => 9582 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 437 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14310399 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/310399
Memory chip and layout design for manufacturing same Jun 19, 2014 Issued
Array ( [id] => 10470822 [patent_doc_number] => 20150355838 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-12-10 [patent_title] => 'ESTIMATING READ REFERENCE VOLTAGE BASED ON DISPARITY AND DERIVATIVE METRICS' [patent_app_type] => utility [patent_app_number] => 14/299195 [patent_app_country] => US [patent_app_date] => 2014-06-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 8431 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14299195 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/299195
Estimating read reference voltage based on disparity and derivative metrics Jun 8, 2014 Issued
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