Search

Douglas King

Examiner (ID: 15404, Phone: (571)272-2311 , Office: P/2824 )

Most Active Art Unit
2824
Art Unit(s)
2824
Total Applications
1004
Issued Applications
774
Pending Applications
71
Abandoned Applications
171

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 11517276 [patent_doc_number] => 20170084350 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-03-23 [patent_title] => 'VALIDATION OF A REPAIR TO A SELECTED ROW OF DATA' [patent_app_type] => utility [patent_app_number] => 15/310629 [patent_app_country] => US [patent_app_date] => 2014-05-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6987 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15310629 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/310629
Validation of a repair to a selected row of data May 26, 2014 Issued
Array ( [id] => 12249935 [patent_doc_number] => 09922718 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-03-20 [patent_title] => 'Flash command that reports a count of cell program failures' [patent_app_type] => utility [patent_app_number] => 14/284875 [patent_app_country] => US [patent_app_date] => 2014-05-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 6570 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 278 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14284875 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/284875
Flash command that reports a count of cell program failures May 21, 2014 Issued
Array ( [id] => 10425897 [patent_doc_number] => 20150310909 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-10-29 [patent_title] => 'OPTIMIZATION OF CIRCUIT LAYOUT AREA OF A MEMORY DEVICE' [patent_app_type] => utility [patent_app_number] => 14/278763 [patent_app_country] => US [patent_app_date] => 2014-05-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 7391 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14278763 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/278763
OPTIMIZATION OF CIRCUIT LAYOUT AREA OF A MEMORY DEVICE May 14, 2014 Abandoned
Array ( [id] => 10556867 [patent_doc_number] => 09281069 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-03-08 [patent_title] => 'Method of programming a nonvolatile memory device' [patent_app_type] => utility [patent_app_number] => 14/274041 [patent_app_country] => US [patent_app_date] => 2014-05-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 24 [patent_no_of_words] => 12826 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 337 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14274041 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/274041
Method of programming a nonvolatile memory device May 8, 2014 Issued
Array ( [id] => 10433044 [patent_doc_number] => 20150318056 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-11-05 [patent_title] => 'MEMORY ARRAY TEST LOGIC' [patent_app_type] => utility [patent_app_number] => 14/266039 [patent_app_country] => US [patent_app_date] => 2014-04-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6079 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14266039 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/266039
Memory array test logic Apr 29, 2014 Issued
Array ( [id] => 10425890 [patent_doc_number] => 20150310901 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-10-29 [patent_title] => 'MEMORY WITH A SLEEP MODE' [patent_app_type] => utility [patent_app_number] => 14/261192 [patent_app_country] => US [patent_app_date] => 2014-04-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6226 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14261192 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/261192
MEMORY WITH A SLEEP MODE Apr 23, 2014 Abandoned
Array ( [id] => 10417908 [patent_doc_number] => 20150302918 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-10-22 [patent_title] => 'WORD LINE DECODERS FOR DUAL RAIL STATIC RANDOM ACCESS MEMORIES' [patent_app_type] => utility [patent_app_number] => 14/258236 [patent_app_country] => US [patent_app_date] => 2014-04-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3822 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14258236 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/258236
WORD LINE DECODERS FOR DUAL RAIL STATIC RANDOM ACCESS MEMORIES Apr 21, 2014 Abandoned
Array ( [id] => 10417892 [patent_doc_number] => 20150302902 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-10-22 [patent_title] => 'WRITE/READ PRIORITY BLOCKING SCHEME USING PARALLEL STATIC ADDRESS DECODE PATH' [patent_app_type] => utility [patent_app_number] => 14/255509 [patent_app_country] => US [patent_app_date] => 2014-04-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3186 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14255509 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/255509
Write/read priority blocking scheme using parallel static address decode path Apr 16, 2014 Issued
Array ( [id] => 11200867 [patent_doc_number] => 09431085 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-08-30 [patent_title] => 'Most activated memory portion handling' [patent_app_type] => utility [patent_app_number] => 14/229225 [patent_app_country] => US [patent_app_date] => 2014-03-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 10079 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14229225 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/229225
Most activated memory portion handling Mar 27, 2014 Issued
Array ( [id] => 10232097 [patent_doc_number] => 20150117091 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-04-30 [patent_title] => 'MULTI-CHANNEL, MULTI-BANK MEMORY WITH WIDE DATA INPUT/OUTPUT' [patent_app_type] => utility [patent_app_number] => 14/228899 [patent_app_country] => US [patent_app_date] => 2014-03-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6000 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14228899 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/228899
Multi-channel, multi-bank memory with wide data input/output Mar 27, 2014 Issued
Array ( [id] => 10525389 [patent_doc_number] => 09251908 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-02-02 [patent_title] => 'Memory kink checking' [patent_app_type] => utility [patent_app_number] => 14/227295 [patent_app_country] => US [patent_app_date] => 2014-03-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 12 [patent_no_of_words] => 12590 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14227295 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/227295
Memory kink checking Mar 26, 2014 Issued
Array ( [id] => 9475787 [patent_doc_number] => 20140133250 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-05-15 [patent_title] => 'CURRENT SENSE AMPLIFIER WITH REPLICA BIAS SCHEME' [patent_app_type] => utility [patent_app_number] => 14/160784 [patent_app_country] => US [patent_app_date] => 2014-01-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 4087 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14160784 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/160784
Current sense amplifier with replica bias scheme Jan 21, 2014 Issued
Array ( [id] => 9475792 [patent_doc_number] => 20140133255 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-05-15 [patent_title] => 'SEMICONDUCTOR DEVICE, REFRESH CONTROL METHOD THEREOF AND COMPUTER SYSTEM' [patent_app_type] => utility [patent_app_number] => 14/161240 [patent_app_country] => US [patent_app_date] => 2014-01-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 26 [patent_no_of_words] => 8893 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14161240 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/161240
Semiconductor device, refresh control method thereof and computer system Jan 21, 2014 Issued
Array ( [id] => 9475785 [patent_doc_number] => 20140133248 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-05-15 [patent_title] => 'APPARATUS AND METHOD TO ADJUST CLOCK DUTY CYCLE OF MEMORY' [patent_app_type] => utility [patent_app_number] => 14/159803 [patent_app_country] => US [patent_app_date] => 2014-01-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 4227 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14159803 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/159803
Apparatus and method to adjust clock duty cycle of memory Jan 20, 2014 Issued
Array ( [id] => 9837707 [patent_doc_number] => 20150029788 [patent_country] => US [patent_kind] => A9 [patent_issue_date] => 2015-01-29 [patent_title] => 'METHODS OF PROGRAMMING MEMORY DEVICES' [patent_app_type] => utility [patent_app_number] => 14/143763 [patent_app_country] => US [patent_app_date] => 2013-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 8252 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14143763 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/143763
Methods of programming memory devices Dec 29, 2013 Issued
Array ( [id] => 9837707 [patent_doc_number] => 20150029788 [patent_country] => US [patent_kind] => A9 [patent_issue_date] => 2015-01-29 [patent_title] => 'METHODS OF PROGRAMMING MEMORY DEVICES' [patent_app_type] => utility [patent_app_number] => 14/143763 [patent_app_country] => US [patent_app_date] => 2013-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 8252 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14143763 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/143763
Methods of programming memory devices Dec 29, 2013 Issued
Array ( [id] => 9395273 [patent_doc_number] => 20140092679 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-04-03 [patent_title] => 'MEMORY DEVICE AND WRITING METHOD THEREOF' [patent_app_type] => utility [patent_app_number] => 14/096091 [patent_app_country] => US [patent_app_date] => 2013-12-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3700 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14096091 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/096091
MEMORY DEVICE AND WRITING METHOD THEREOF Dec 3, 2013 Abandoned
Array ( [id] => 10261483 [patent_doc_number] => 20150146480 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-05-28 [patent_title] => 'NOVEL 3D STRUCTURE FOR ADVANCED SRAM DESIGN TO AVOID HALF-SELECTED ISSUE' [patent_app_type] => utility [patent_app_number] => 14/087029 [patent_app_country] => US [patent_app_date] => 2013-11-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4284 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14087029 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/087029
3D structure for advanced SRAM design to avoid half-selected issue Nov 21, 2013 Issued
Array ( [id] => 10189430 [patent_doc_number] => 09218856 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-12-22 [patent_title] => 'Circuits, architectures, apparatuses, systems, algorithms, and methods for memory with multiple power supplies and/or multiple low power modes' [patent_app_type] => utility [patent_app_number] => 14/077634 [patent_app_country] => US [patent_app_date] => 2013-11-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 17 [patent_no_of_words] => 14481 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 269 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14077634 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/077634
Circuits, architectures, apparatuses, systems, algorithms, and methods for memory with multiple power supplies and/or multiple low power modes Nov 11, 2013 Issued
Array ( [id] => 11925395 [patent_doc_number] => 09792980 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-10-17 [patent_title] => 'Three dimensional resistive memory architectures' [patent_app_type] => utility [patent_app_number] => 15/031813 [patent_app_country] => US [patent_app_date] => 2013-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 15 [patent_no_of_words] => 6179 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 178 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15031813 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/031813
Three dimensional resistive memory architectures Oct 30, 2013 Issued
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