Search

Douglas King

Examiner (ID: 15404, Phone: (571)272-2311 , Office: P/2824 )

Most Active Art Unit
2824
Art Unit(s)
2824
Total Applications
1004
Issued Applications
774
Pending Applications
71
Abandoned Applications
171

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 9583932 [patent_doc_number] => 08773938 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-07-08 [patent_title] => 'Semiconductor device' [patent_app_type] => utility [patent_app_number] => 13/064915 [patent_app_country] => US [patent_app_date] => 2011-04-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4741 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 164 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13064915 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/064915
Semiconductor device Apr 25, 2011 Issued
Array ( [id] => 9101139 [patent_doc_number] => 08565028 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-10-22 [patent_title] => 'Semiconductor nonvolatile memory device' [patent_app_type] => utility [patent_app_number] => 13/093467 [patent_app_country] => US [patent_app_date] => 2011-04-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 17 [patent_no_of_words] => 10382 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 190 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13093467 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/093467
Semiconductor nonvolatile memory device Apr 24, 2011 Issued
Array ( [id] => 6163467 [patent_doc_number] => 20110194363 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-08-11 [patent_title] => 'SEMICONDUCTOR MEMORY CELL AND ARRAY USING PUNCH-THROUGH TO PROGRAM AND READ SAME' [patent_app_type] => utility [patent_app_number] => 13/092704 [patent_app_country] => US [patent_app_date] => 2011-04-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 9698 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0194/20110194363.pdf [firstpage_image] =>[orig_patent_app_number] => 13092704 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/092704
Semiconductor memory cell and array using punch-through to program and read same Apr 21, 2011 Issued
Array ( [id] => 8463841 [patent_doc_number] => 20120269009 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-10-25 [patent_title] => 'MEMORY ARRAY WITH TWO-PHASE BIT LINE PRECHARGE' [patent_app_type] => utility [patent_app_number] => 13/089835 [patent_app_country] => US [patent_app_date] => 2011-04-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4872 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13089835 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/089835
Memory array with two-phase bit line precharge Apr 18, 2011 Issued
Array ( [id] => 8452051 [patent_doc_number] => 20120262997 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-10-18 [patent_title] => 'METHOD FOR SEARCHING OPTIMUM VALUE OF MEMORY' [patent_app_type] => utility [patent_app_number] => 13/085795 [patent_app_country] => US [patent_app_date] => 2011-04-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 8408 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13085795 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/085795
Method for searching optimum value of memory Apr 12, 2011 Issued
Array ( [id] => 8300254 [patent_doc_number] => 20120182806 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-07-19 [patent_title] => 'Memory Architecture of 3D Array With Alternating Memory String Orientation and String Select Structures' [patent_app_type] => utility [patent_app_number] => 13/078311 [patent_app_country] => US [patent_app_date] => 2011-04-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 31 [patent_figures_cnt] => 31 [patent_no_of_words] => 12025 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13078311 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/078311
Memory architecture of 3D array with alternating memory string orientation and string select structures Mar 31, 2011 Issued
Array ( [id] => 9346511 [patent_doc_number] => 08665665 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-03-04 [patent_title] => 'Apparatus and method to adjust clock duty cycle of memory' [patent_app_type] => utility [patent_app_number] => 13/076023 [patent_app_country] => US [patent_app_date] => 2011-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 4195 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13076023 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/076023
Apparatus and method to adjust clock duty cycle of memory Mar 29, 2011 Issued
Array ( [id] => 8415864 [patent_doc_number] => 20120243364 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-09-27 [patent_title] => 'METHOD AND SYSTEM FOR DYNAMIC POWER MANAGEMENT OF MEMORIES' [patent_app_type] => utility [patent_app_number] => 13/069647 [patent_app_country] => US [patent_app_date] => 2011-03-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4434 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13069647 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/069647
Method and system for dynamic power management of memories Mar 22, 2011 Issued
Array ( [id] => 8039905 [patent_doc_number] => 20120069684 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-03-22 [patent_title] => 'SEMICONDUCTOR INTEGRATED CIRCUIT' [patent_app_type] => utility [patent_app_number] => 13/053443 [patent_app_country] => US [patent_app_date] => 2011-03-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 6942 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0069/20120069684.pdf [firstpage_image] =>[orig_patent_app_number] => 13053443 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/053443
SEMICONDUCTOR INTEGRATED CIRCUIT Mar 21, 2011 Abandoned
Array ( [id] => 7697984 [patent_doc_number] => 20110228606 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-09-22 [patent_title] => 'NONVOLATILE SEMICONDUCTOR MEMORY DEVICE' [patent_app_type] => utility [patent_app_number] => 13/050687 [patent_app_country] => US [patent_app_date] => 2011-03-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5920 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0228/20110228606.pdf [firstpage_image] =>[orig_patent_app_number] => 13050687 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/050687
NONVOLATILE SEMICONDUCTOR MEMORY DEVICE Mar 16, 2011 Abandoned
Array ( [id] => 9217308 [patent_doc_number] => 08630114 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-01-14 [patent_title] => 'Memory architecture of 3D NOR array' [patent_app_type] => utility [patent_app_number] => 13/045975 [patent_app_country] => US [patent_app_date] => 2011-03-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 25 [patent_no_of_words] => 8754 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 155 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13045975 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/045975
Memory architecture of 3D NOR array Mar 10, 2011 Issued
Array ( [id] => 6020183 [patent_doc_number] => 20110225355 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-09-15 [patent_title] => 'SEMICONDUCTOR DEVICE, REFRESH CONTROL METHOD THEREOF AND COMPUTER SYSTEM' [patent_app_type] => utility [patent_app_number] => 13/044111 [patent_app_country] => US [patent_app_date] => 2011-03-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 26 [patent_no_of_words] => 8853 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0225/20110225355.pdf [firstpage_image] =>[orig_patent_app_number] => 13044111 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/044111
SEMICONDUCTOR DEVICE, REFRESH CONTROL METHOD THEREOF AND COMPUTER SYSTEM Mar 8, 2011 Abandoned
Array ( [id] => 6044807 [patent_doc_number] => 20110205802 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-08-25 [patent_title] => 'NONVOLATILE MEMORY DEVICE AND METHOD OF READING THE SAME' [patent_app_type] => utility [patent_app_number] => 13/029947 [patent_app_country] => US [patent_app_date] => 2011-02-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 14380 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0205/20110205802.pdf [firstpage_image] =>[orig_patent_app_number] => 13029947 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/029947
NONVOLATILE MEMORY DEVICE AND METHOD OF READING THE SAME Feb 16, 2011 Abandoned
Array ( [id] => 8346064 [patent_doc_number] => 20120206983 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-08-16 [patent_title] => 'TRACKING SCHEME FOR MEMORY' [patent_app_type] => utility [patent_app_number] => 13/026021 [patent_app_country] => US [patent_app_date] => 2011-02-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 1987 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13026021 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/026021
Tracking scheme for memory Feb 10, 2011 Issued
Array ( [id] => 10884047 [patent_doc_number] => 08908434 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-12-09 [patent_title] => 'Operating methods of flash memory and decoding circuits thereof' [patent_app_type] => utility [patent_app_number] => 13/021381 [patent_app_country] => US [patent_app_date] => 2011-02-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4565 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 189 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13021381 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/021381
Operating methods of flash memory and decoding circuits thereof Feb 3, 2011 Issued
Array ( [id] => 8322728 [patent_doc_number] => 20120195141 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-08-02 [patent_title] => 'GENERIC LOW POWER STROBE BASED SYSTEM AND METHOD FOR INTERFACING MEMORY CONTROLLER AND SOURCE SYNCHRONOUS MEMORY' [patent_app_type] => utility [patent_app_number] => 13/016071 [patent_app_country] => US [patent_app_date] => 2011-01-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 3900 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13016071 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/016071
Generic low power strobe based system and method for interfacing memory controller and source synchronous memory Jan 27, 2011 Issued
Array ( [id] => 6108621 [patent_doc_number] => 20110188332 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-08-04 [patent_title] => 'Semiconductor memory device having regular area and spare area' [patent_app_type] => utility [patent_app_number] => 12/929483 [patent_app_country] => US [patent_app_date] => 2011-01-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 7725 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0188/20110188332.pdf [firstpage_image] =>[orig_patent_app_number] => 12929483 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/929483
Semiconductor memory device having regular area and spare area Jan 27, 2011 Issued
Array ( [id] => 8622357 [patent_doc_number] => 08355273 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-01-15 [patent_title] => 'Variable-resistance material memories, processes of forming same, and methods of using same' [patent_app_type] => utility [patent_app_number] => 12/986717 [patent_app_country] => US [patent_app_date] => 2011-01-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 13 [patent_no_of_words] => 6688 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12986717 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/986717
Variable-resistance material memories, processes of forming same, and methods of using same Jan 6, 2011 Issued
Array ( [id] => 6163460 [patent_doc_number] => 20110194357 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-08-11 [patent_title] => 'NONVOLATILE MEMORY DEVICES, OPERATING METHODS THEREOF AND MEMORY SYSTEMS INCLUDING THE SAME' [patent_app_type] => utility [patent_app_number] => 12/985695 [patent_app_country] => US [patent_app_date] => 2011-01-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 31 [patent_figures_cnt] => 31 [patent_no_of_words] => 14081 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0194/20110194357.pdf [firstpage_image] =>[orig_patent_app_number] => 12985695 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/985695
Nonvolatile memory devices, operating methods thereof and memory systems including the same Jan 5, 2011 Issued
Array ( [id] => 8169461 [patent_doc_number] => 20120106262 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-05-03 [patent_title] => 'PROGRAMMING METHOD FOR NONVOLATILE MEMORY APPARATUS' [patent_app_type] => utility [patent_app_number] => 12/983105 [patent_app_country] => US [patent_app_date] => 2010-12-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3439 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0106/20120106262.pdf [firstpage_image] =>[orig_patent_app_number] => 12983105 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/983105
Programming method for nonvolatile memory apparatus Dec 30, 2010 Issued
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