
Douglas King
Examiner (ID: 15404, Phone: (571)272-2311 , Office: P/2824 )
| Most Active Art Unit | 2824 |
| Art Unit(s) | 2824 |
| Total Applications | 1004 |
| Issued Applications | 774 |
| Pending Applications | 71 |
| Abandoned Applications | 171 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 7719114
[patent_doc_number] => 20120008449
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2012-01-12
[patent_title] => 'LOW POWER STATIC RANDOM ACCESS MEMORY'
[patent_app_type] => utility
[patent_app_number] => 12/979345
[patent_app_country] => US
[patent_app_date] => 2010-12-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 15
[patent_figures_cnt] => 15
[patent_no_of_words] => 5577
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0008/20120008449.pdf
[firstpage_image] =>[orig_patent_app_number] => 12979345
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/979345 | Low power static random access memory | Dec 27, 2010 | Issued |
Array
(
[id] => 8263683
[patent_doc_number] => 20120163110
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2012-06-28
[patent_title] => 'MEMORY DEVICE WITH ROBUST WRITE ASSIST'
[patent_app_type] => utility
[patent_app_number] => 12/979757
[patent_app_country] => US
[patent_app_date] => 2010-12-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 7113
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12979757
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/979757 | Memory device with robust write assist | Dec 27, 2010 | Issued |
Array
(
[id] => 8803562
[patent_doc_number] => 08441842
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2013-05-14
[patent_title] => 'Memory device having memory cells with enhanced low voltage write capability'
[patent_app_type] => utility
[patent_app_number] => 12/974441
[patent_app_country] => US
[patent_app_date] => 2010-12-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 8
[patent_no_of_words] => 4967
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 211
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12974441
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/974441 | Memory device having memory cells with enhanced low voltage write capability | Dec 20, 2010 | Issued |
Array
(
[id] => 7969965
[patent_doc_number] => 07940557
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2011-05-10
[patent_title] => 'Non-volatile electromechanical configuration bit array'
[patent_app_type] => utility
[patent_app_number] => 12/974737
[patent_app_country] => US
[patent_app_date] => 2010-12-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 14
[patent_figures_cnt] => 15
[patent_no_of_words] => 8228
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 308
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/940/07940557.pdf
[firstpage_image] =>[orig_patent_app_number] => 12974737
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/974737 | Non-volatile electromechanical configuration bit array | Dec 20, 2010 | Issued |
Array
(
[id] => 6157341
[patent_doc_number] => 20110157976
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2011-06-30
[patent_title] => 'Voltage Stabilization Device and Semiconductor Device Including the Same, and Voltage Generation Method'
[patent_app_type] => utility
[patent_app_number] => 12/971339
[patent_app_country] => US
[patent_app_date] => 2010-12-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 16
[patent_figures_cnt] => 16
[patent_no_of_words] => 8789
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0157/20110157976.pdf
[firstpage_image] =>[orig_patent_app_number] => 12971339
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/971339 | Voltage stabilization device and semiconductor device including the same, and voltage generation method | Dec 16, 2010 | Issued |
Array
(
[id] => 8226352
[patent_doc_number] => 20120140556
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2012-06-07
[patent_title] => 'METHOD OF OPERATING FLASH MEMORY'
[patent_app_type] => utility
[patent_app_number] => 12/961847
[patent_app_country] => US
[patent_app_date] => 2010-12-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 2547
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12961847
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/961847 | METHOD OF OPERATING FLASH MEMORY | Dec 6, 2010 | Abandoned |
Array
(
[id] => 8226332
[patent_doc_number] => 20120140541
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2012-06-07
[patent_title] => 'MEMORY BUILT-IN SELF TEST SCHEME FOR CONTENT ADDRESSABLE MEMORY ARRAY'
[patent_app_type] => utility
[patent_app_number] => 12/958539
[patent_app_country] => US
[patent_app_date] => 2010-12-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 3575
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12958539
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/958539 | MEMORY BUILT-IN SELF TEST SCHEME FOR CONTENT ADDRESSABLE MEMORY ARRAY | Dec 1, 2010 | Abandoned |
Array
(
[id] => 6140503
[patent_doc_number] => 20110128785
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2011-06-02
[patent_title] => 'APPARATUS AND METHOD FOR PROTECTING DATA IN FLASH MEMORY'
[patent_app_type] => utility
[patent_app_number] => 12/954717
[patent_app_country] => US
[patent_app_date] => 2010-11-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 5419
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0128/20110128785.pdf
[firstpage_image] =>[orig_patent_app_number] => 12954717
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/954717 | Apparatus and method for protecting data in flash memory | Nov 25, 2010 | Issued |
Array
(
[id] => 7578857
[patent_doc_number] => 20110292740
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2011-12-01
[patent_title] => 'SEMICONDUCTOR DEVICE AND METHOD FOR OPERATING THE SAME'
[patent_app_type] => utility
[patent_app_number] => 12/949143
[patent_app_country] => US
[patent_app_date] => 2010-11-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 10
[patent_no_of_words] => 5933
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0292/20110292740.pdf
[firstpage_image] =>[orig_patent_app_number] => 12949143
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/949143 | SEMICONDUCTOR DEVICE AND METHOD FOR OPERATING THE SAME | Nov 17, 2010 | Abandoned |
Array
(
[id] => 5999260
[patent_doc_number] => 20110116299
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2011-05-19
[patent_title] => 'SEMICONDUCTOR DEVICE'
[patent_app_type] => utility
[patent_app_number] => 12/938001
[patent_app_country] => US
[patent_app_date] => 2010-11-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 41
[patent_figures_cnt] => 41
[patent_no_of_words] => 24677
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0116/20110116299.pdf
[firstpage_image] =>[orig_patent_app_number] => 12938001
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/938001 | Semiconductor device | Nov 1, 2010 | Issued |
Array
(
[id] => 6069257
[patent_doc_number] => 20110044106
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2011-02-24
[patent_title] => 'NONVOLATILE SEMICONDUCTOR MEMORY AND DATA READING METHOD'
[patent_app_type] => utility
[patent_app_number] => 12/916856
[patent_app_country] => US
[patent_app_date] => 2010-11-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 35
[patent_figures_cnt] => 35
[patent_no_of_words] => 18424
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 6
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0044/20110044106.pdf
[firstpage_image] =>[orig_patent_app_number] => 12916856
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/916856 | Nonvolatile semiconductor memory and data reading method | Oct 31, 2010 | Issued |
Array
(
[id] => 8934102
[patent_doc_number] => 08493812
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2013-07-23
[patent_title] => 'Boost circuit for generating an adjustable boost voltage'
[patent_app_type] => utility
[patent_app_number] => 12/913929
[patent_app_country] => US
[patent_app_date] => 2010-10-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 6935
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 131
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12913929
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/913929 | Boost circuit for generating an adjustable boost voltage | Oct 27, 2010 | Issued |
Array
(
[id] => 9228594
[patent_doc_number] => 08634268
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2014-01-21
[patent_title] => 'Memory circuit having decoding circuits and method of operating the same'
[patent_app_type] => utility
[patent_app_number] => 12/912971
[patent_app_country] => US
[patent_app_date] => 2010-10-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 3767
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 204
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12912971
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/912971 | Memory circuit having decoding circuits and method of operating the same | Oct 26, 2010 | Issued |
Array
(
[id] => 6189203
[patent_doc_number] => 20110125966
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2011-05-26
[patent_title] => 'MULTI-RANK MEMORY MODULE THAT EMULATES A MEMORY MODULE HAVING A DIFFERENT NUMBER OF RANKS'
[patent_app_type] => utility
[patent_app_number] => 12/902073
[patent_app_country] => US
[patent_app_date] => 2010-10-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 11
[patent_no_of_words] => 5022
[patent_no_of_claims] => 92
[patent_no_of_ind_claims] => 8
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0125/20110125966.pdf
[firstpage_image] =>[orig_patent_app_number] => 12902073
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/902073 | Multi-rank memory module that emulates a memory module having a different number of ranks | Oct 10, 2010 | Issued |
Array
(
[id] => 6147841
[patent_doc_number] => 20110019472
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2011-01-27
[patent_title] => 'NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND PROGRAMMING METHOD THEREOF'
[patent_app_type] => utility
[patent_app_number] => 12/899884
[patent_app_country] => US
[patent_app_date] => 2010-10-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 6401
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0019/20110019472.pdf
[firstpage_image] =>[orig_patent_app_number] => 12899884
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/899884 | Nonvolatile semiconductor memory device and programming method thereof | Oct 6, 2010 | Issued |
Array
(
[id] => 8092711
[patent_doc_number] => 20120081962
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2012-04-05
[patent_title] => 'LOW VOLTAGE PROGRAMMING IN NAND FLASH'
[patent_app_type] => utility
[patent_app_number] => 12/898979
[patent_app_country] => US
[patent_app_date] => 2010-10-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 19
[patent_figures_cnt] => 19
[patent_no_of_words] => 10770
[patent_no_of_claims] => 25
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0081/20120081962.pdf
[firstpage_image] =>[orig_patent_app_number] => 12898979
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/898979 | Low voltage programming in NAND flash | Oct 5, 2010 | Issued |
Array
(
[id] => 6194572
[patent_doc_number] => 20110026326
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2011-02-03
[patent_title] => 'MEMORY SYSTEM INCLUDING FLASH MEMORY AND METHOD OF OPERATING THE SAME'
[patent_app_type] => utility
[patent_app_number] => 12/897869
[patent_app_country] => US
[patent_app_date] => 2010-10-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 10
[patent_no_of_words] => 5303
[patent_no_of_claims] => 1
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0026/20110026326.pdf
[firstpage_image] =>[orig_patent_app_number] => 12897869
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/897869 | MEMORY SYSTEM INCLUDING FLASH MEMORY AND METHOD OF OPERATING THE SAME | Oct 4, 2010 | Abandoned |
Array
(
[id] => 6029392
[patent_doc_number] => 20110080773
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2011-04-07
[patent_title] => 'CIRCUIT FOR GENERATING ADJUSTABLE TIMING SIGNALS FOR SENSING A SELF-REFERENCED MRAM CELL'
[patent_app_type] => utility
[patent_app_number] => 12/888643
[patent_app_country] => US
[patent_app_date] => 2010-09-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 6073
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0080/20110080773.pdf
[firstpage_image] =>[orig_patent_app_number] => 12888643
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/888643 | Circuit for generating adjustable timing signals for sensing a self-referenced MRAM cell | Sep 22, 2010 | Issued |
Array
(
[id] => 6147793
[patent_doc_number] => 20110019459
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2011-01-27
[patent_title] => 'Three-Dimensional Mask-Programmable Read-Only Memory with Reserved Space'
[patent_app_type] => utility
[patent_app_number] => 12/883172
[patent_app_country] => US
[patent_app_date] => 2010-09-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 2833
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0019/20110019459.pdf
[firstpage_image] =>[orig_patent_app_number] => 12883172
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/883172 | Three-Dimensional Mask-Programmable Read-Only Memory with Reserved Space | Sep 14, 2010 | Abandoned |
Array
(
[id] => 6006078
[patent_doc_number] => 20110058439
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2011-03-10
[patent_title] => 'Circuits, Architectures, Apparatuses, Systems, Algorithms, and Methods for Memory with Multiple Power Supplies and/or Multiple Low Power Modes'
[patent_app_type] => utility
[patent_app_number] => 12/878703
[patent_app_country] => US
[patent_app_date] => 2010-09-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 12
[patent_no_of_words] => 14416
[patent_no_of_claims] => 26
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0058/20110058439.pdf
[firstpage_image] =>[orig_patent_app_number] => 12878703
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/878703 | Circuits, architectures, apparatuses, systems, algorithms, and methods for memory with multiple power supplies and/or multiple low power modes | Sep 8, 2010 | Issued |