Search

Douglas King

Examiner (ID: 15404, Phone: (571)272-2311 , Office: P/2824 )

Most Active Art Unit
2824
Art Unit(s)
2824
Total Applications
1004
Issued Applications
774
Pending Applications
71
Abandoned Applications
171

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 6108540 [patent_doc_number] => 20110188302 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-08-04 [patent_title] => 'METHOD OF DRIVING PHASE CHANGE MEMORY DEVICE CAPABLE OF REDUCING HEAT DISTURBANCE' [patent_app_type] => utility [patent_app_number] => 12/782849 [patent_app_country] => US [patent_app_date] => 2010-05-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2122 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0188/20110188302.pdf [firstpage_image] =>[orig_patent_app_number] => 12782849 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/782849
METHOD OF DRIVING PHASE CHANGE MEMORY DEVICE CAPABLE OF REDUCING HEAT DISTURBANCE May 18, 2010 Abandoned
Array ( [id] => 9168180 [patent_doc_number] => 08593864 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-11-26 [patent_title] => 'Nonvolatile memory device and method of programming the same' [patent_app_type] => utility [patent_app_number] => 12/765349 [patent_app_country] => US [patent_app_date] => 2010-04-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 3773 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12765349 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/765349
Nonvolatile memory device and method of programming the same Apr 21, 2010 Issued
Array ( [id] => 8761761 [patent_doc_number] => 08422291 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-04-16 [patent_title] => 'Storage device and method for reading the same' [patent_app_type] => utility [patent_app_number] => 12/662329 [patent_app_country] => US [patent_app_date] => 2010-04-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 22 [patent_no_of_words] => 7472 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 171 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12662329 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/662329
Storage device and method for reading the same Apr 11, 2010 Issued
Array ( [id] => 7482758 [patent_doc_number] => 20110249515 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-10-13 [patent_title] => 'DIMM Memory Module Reference Voltage Switching Circuit' [patent_app_type] => utility [patent_app_number] => 12/756439 [patent_app_country] => US [patent_app_date] => 2010-04-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 4931 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0249/20110249515.pdf [firstpage_image] =>[orig_patent_app_number] => 12756439 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/756439
DIMM memory module reference voltage switching circuit Apr 7, 2010 Issued
Array ( [id] => 6494857 [patent_doc_number] => 20100259984 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-10-14 [patent_title] => 'ERASE METHOD OF NONVOLATILE SEMICONDUCTOR MEMORY DEVICE' [patent_app_type] => utility [patent_app_number] => 12/752573 [patent_app_country] => US [patent_app_date] => 2010-04-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 6527 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0259/20100259984.pdf [firstpage_image] =>[orig_patent_app_number] => 12752573 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/752573
ERASE METHOD OF NONVOLATILE SEMICONDUCTOR MEMORY DEVICE Mar 31, 2010 Abandoned
Array ( [id] => 6147862 [patent_doc_number] => 20110019486 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-01-27 [patent_title] => 'SEMICONDUCTOR MEMORY DEVICE AND PROGRAMMING METHOD THEREOF' [patent_app_type] => utility [patent_app_number] => 12/748613 [patent_app_country] => US [patent_app_date] => 2010-03-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 15277 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0019/20110019486.pdf [firstpage_image] =>[orig_patent_app_number] => 12748613 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/748613
Semiconductor memory device and programming method thereof Mar 28, 2010 Issued
Array ( [id] => 6227621 [patent_doc_number] => 20100182821 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-07-22 [patent_title] => 'MEMORY DEVICE, MEMORY CIRCUIT AND SEMICONDUCTOR INTEGRATED CIRCUIT HAVING VARIABLE RESISTANCE' [patent_app_type] => utility [patent_app_number] => 12/749296 [patent_app_country] => US [patent_app_date] => 2010-03-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 31 [patent_figures_cnt] => 31 [patent_no_of_words] => 19824 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0182/20100182821.pdf [firstpage_image] =>[orig_patent_app_number] => 12749296 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/749296
MEMORY DEVICE, MEMORY CIRCUIT AND SEMICONDUCTOR INTEGRATED CIRCUIT HAVING VARIABLE RESISTANCE Mar 28, 2010 Abandoned
Array ( [id] => 7697970 [patent_doc_number] => 20110228620 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-09-22 [patent_title] => 'TESTING METHOD FOR SEMICONDUCTOR MEMORY DEVICE' [patent_app_type] => utility [patent_app_number] => 12/728847 [patent_app_country] => US [patent_app_date] => 2010-03-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 2913 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0228/20110228620.pdf [firstpage_image] =>[orig_patent_app_number] => 12728847 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/728847
TESTING METHOD FOR SEMICONDUCTOR MEMORY DEVICE Mar 21, 2010 Abandoned
Array ( [id] => 8459442 [patent_doc_number] => 08295118 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-10-23 [patent_title] => 'Self-timed interface for strobe-based systems' [patent_app_type] => utility [patent_app_number] => 12/721520 [patent_app_country] => US [patent_app_date] => 2010-03-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6328 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12721520 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/721520
Self-timed interface for strobe-based systems Mar 9, 2010 Issued
Array ( [id] => 6421111 [patent_doc_number] => 20100142252 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-06-10 [patent_title] => 'RECONFIGURABLE INPUT/OUTPUT IN HIERARCHICAL MEMORY LINK' [patent_app_type] => utility [patent_app_number] => 12/708049 [patent_app_country] => US [patent_app_date] => 2010-02-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 4847 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0142/20100142252.pdf [firstpage_image] =>[orig_patent_app_number] => 12708049 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/708049
Reconfigurable input/output in hierarchical memory link Feb 17, 2010 Issued
Array ( [id] => 6484026 [patent_doc_number] => 20100208531 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-08-19 [patent_title] => 'DATA READING CIRCUIT' [patent_app_type] => utility [patent_app_number] => 12/705791 [patent_app_country] => US [patent_app_date] => 2010-02-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2412 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0208/20100208531.pdf [firstpage_image] =>[orig_patent_app_number] => 12705791 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/705791
DATA READING CIRCUIT Feb 14, 2010 Abandoned
Array ( [id] => 6412018 [patent_doc_number] => 20100149885 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-06-17 [patent_title] => 'Memory circuit and method of writing data to and reading data from memory circuit' [patent_app_type] => utility [patent_app_number] => 12/656697 [patent_app_country] => US [patent_app_date] => 2010-02-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6869 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0149/20100149885.pdf [firstpage_image] =>[orig_patent_app_number] => 12656697 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/656697
Memory circuit and method of writing data to and reading data from memory circuit Feb 11, 2010 Issued
Array ( [id] => 7980075 [patent_doc_number] => 08072790 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-12-06 [patent_title] => 'High speed FRAM including a deselect circuit' [patent_app_type] => utility [patent_app_number] => 12/701547 [patent_app_country] => US [patent_app_date] => 2010-02-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 22 [patent_no_of_words] => 13396 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 387 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/072/08072790.pdf [firstpage_image] =>[orig_patent_app_number] => 12701547 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/701547
High speed FRAM including a deselect circuit Feb 5, 2010 Issued
Array ( [id] => 7551905 [patent_doc_number] => 08064242 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-11-22 [patent_title] => 'Very high speed FRAM for replacing SRAM' [patent_app_type] => utility [patent_app_number] => 12/699815 [patent_app_country] => US [patent_app_date] => 2010-02-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 20 [patent_no_of_words] => 11628 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 346 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/064/08064242.pdf [firstpage_image] =>[orig_patent_app_number] => 12699815 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/699815
Very high speed FRAM for replacing SRAM Feb 2, 2010 Issued
Array ( [id] => 6316583 [patent_doc_number] => 20100195411 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-08-05 [patent_title] => 'SEMICONDUCTOR MEMORY DEVICE AND FAIL BIT DETECTION METHOD IN SEMICONDUCTOR MEMORY DEVICE' [patent_app_type] => utility [patent_app_number] => 12/694605 [patent_app_country] => US [patent_app_date] => 2010-01-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 5327 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0195/20100195411.pdf [firstpage_image] =>[orig_patent_app_number] => 12694605 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/694605
SEMICONDUCTOR MEMORY DEVICE AND FAIL BIT DETECTION METHOD IN SEMICONDUCTOR MEMORY DEVICE Jan 26, 2010 Abandoned
Array ( [id] => 6316494 [patent_doc_number] => 20100195387 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-08-05 [patent_title] => 'NON-VOLATILE MEMORY DEVICE AND ISPP PROGRAMMING METHOD' [patent_app_type] => utility [patent_app_number] => 12/690995 [patent_app_country] => US [patent_app_date] => 2010-01-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 8182 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0195/20100195387.pdf [firstpage_image] =>[orig_patent_app_number] => 12690995 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/690995
NON-VOLATILE MEMORY DEVICE AND ISPP PROGRAMMING METHOD Jan 20, 2010 Abandoned
Array ( [id] => 6186324 [patent_doc_number] => 20110170353 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-07-14 [patent_title] => 'ACCESS LINE DEPENDENT BIASING SCHEMES' [patent_app_type] => utility [patent_app_number] => 12/686721 [patent_app_country] => US [patent_app_date] => 2010-01-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 8065 [patent_no_of_claims] => 45 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0170/20110170353.pdf [firstpage_image] =>[orig_patent_app_number] => 12686721 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/686721
Access line dependent biasing schemes Jan 12, 2010 Issued
Array ( [id] => 6530224 [patent_doc_number] => 20100124104 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-05-20 [patent_title] => 'Memory device and writing method thereof' [patent_app_type] => utility [patent_app_number] => 12/591295 [patent_app_country] => US [patent_app_date] => 2009-11-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3674 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0124/20100124104.pdf [firstpage_image] =>[orig_patent_app_number] => 12591295 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/591295
Memory device and writing method thereof Nov 15, 2009 Issued
Array ( [id] => 8295772 [patent_doc_number] => 08223568 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-07-17 [patent_title] => 'Semiconductor memory device adopting improved local input/output line precharging scheme' [patent_app_type] => utility [patent_app_number] => 12/588535 [patent_app_country] => US [patent_app_date] => 2009-10-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6715 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 173 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12588535 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/588535
Semiconductor memory device adopting improved local input/output line precharging scheme Oct 18, 2009 Issued
Array ( [id] => 6123460 [patent_doc_number] => 20110085390 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-04-14 [patent_title] => 'WORD-LINE LEVEL SHIFT CIRCUIT' [patent_app_type] => utility [patent_app_number] => 12/579089 [patent_app_country] => US [patent_app_date] => 2009-10-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2273 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0085/20110085390.pdf [firstpage_image] =>[orig_patent_app_number] => 12579089 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/579089
Word-line level shift circuit Oct 13, 2009 Issued
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