Search

Douglas King

Examiner (ID: 126, Phone: (571)272-2311 , Office: P/2824 )

Most Active Art Unit
2824
Art Unit(s)
2824
Total Applications
970
Issued Applications
746
Pending Applications
78
Abandoned Applications
170

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 19500126 [patent_doc_number] => 20240339144 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-10 [patent_title] => Magnetoresistive Random-Access Memory (MRAM) Cell and Method of Operation Thereof [patent_app_type] => utility [patent_app_number] => 18/364674 [patent_app_country] => US [patent_app_date] => 2023-08-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10969 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18364674 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/364674
Magnetoresistive Random-Access Memory (MRAM) Cell and Method of Operation Thereof Aug 2, 2023 Pending
Array ( [id] => 20389111 [patent_doc_number] => 12488844 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-12-02 [patent_title] => Systems and methods to avoid over programming at infrequent smart verify acquisition for high-performance 3D NAND [patent_app_type] => utility [patent_app_number] => 18/229873 [patent_app_country] => US [patent_app_date] => 2023-08-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 24 [patent_no_of_words] => 7129 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18229873 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/229873
Systems and methods to avoid over programming at infrequent smart verify acquisition for high-performance 3D NAND Aug 2, 2023 Issued
Array ( [id] => 19696086 [patent_doc_number] => 20250014631 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-01-09 [patent_title] => MEMORY DEVICE AND OPERATING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 18/364094 [patent_app_country] => US [patent_app_date] => 2023-08-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9996 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 155 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18364094 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/364094
Memory device and operating method thereof Aug 1, 2023 Issued
Array ( [id] => 19559652 [patent_doc_number] => 20240371444 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-11-07 [patent_title] => ASYMMETRIC VREADK TO REDUCE NEIGHBORING WORD LINE INTERFERENCE IN A MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 18/228795 [patent_app_country] => US [patent_app_date] => 2023-08-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14307 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18228795 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/228795
Asymmetric VREADK to reduce neighboring word line interference in a memory device Jul 31, 2023 Issued
Array ( [id] => 19757821 [patent_doc_number] => 20250046386 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-02-06 [patent_title] => NON-VOLATILE MEMORY WITH HIGH PERFORMANCE READ [patent_app_type] => utility [patent_app_number] => 18/362509 [patent_app_country] => US [patent_app_date] => 2023-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 22947 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18362509 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/362509
NON-VOLATILE MEMORY WITH HIGH PERFORMANCE READ Jul 30, 2023 Pending
Array ( [id] => 19757821 [patent_doc_number] => 20250046386 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-02-06 [patent_title] => NON-VOLATILE MEMORY WITH HIGH PERFORMANCE READ [patent_app_type] => utility [patent_app_number] => 18/362509 [patent_app_country] => US [patent_app_date] => 2023-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 22947 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18362509 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/362509
NON-VOLATILE MEMORY WITH HIGH PERFORMANCE READ Jul 30, 2023 Pending
Array ( [id] => 18925250 [patent_doc_number] => 20240028254 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-01-25 [patent_title] => COMPUTING-IN-MEMORY DEVICE AND METHOD [patent_app_type] => utility [patent_app_number] => 18/362667 [patent_app_country] => US [patent_app_date] => 2023-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3614 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18362667 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/362667
COMPUTING-IN-MEMORY DEVICE AND METHOD Jul 30, 2023 Pending
Array ( [id] => 19070833 [patent_doc_number] => 20240105259 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-03-28 [patent_title] => PSEUDO MULTI-PORT MEMORY WITH MEMORY CELLS EACH HAVING TWO-PORT MEMORY CELL ARCHITECTURE AND MULTIPLE ENABLE PULSES ON SAME WORDLINE AND ASSOCIATED MEMORY ACCESS METHOD [patent_app_type] => utility [patent_app_number] => 18/228621 [patent_app_country] => US [patent_app_date] => 2023-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3339 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18228621 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/228621
PSEUDO MULTI-PORT MEMORY WITH MEMORY CELLS EACH HAVING TWO-PORT MEMORY CELL ARCHITECTURE AND MULTIPLE ENABLE PULSES ON SAME WORDLINE AND ASSOCIATED MEMORY ACCESS METHOD Jul 30, 2023 Pending
Array ( [id] => 19628737 [patent_doc_number] => 12167613 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-12-10 [patent_title] => Circuit and method to enhance efficiency of memory [patent_app_type] => utility [patent_app_number] => 18/361897 [patent_app_country] => US [patent_app_date] => 2023-07-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6339 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18361897 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/361897
Circuit and method to enhance efficiency of memory Jul 29, 2023 Issued
Array ( [id] => 19618902 [patent_doc_number] => 20240404582 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-12-05 [patent_title] => MEMORY CONTROLLER SUPPORT FOR MIXED READ [patent_app_type] => utility [patent_app_number] => 18/360096 [patent_app_country] => US [patent_app_date] => 2023-07-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13151 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18360096 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/360096
Memory controller support for mixed read Jul 26, 2023 Issued
Array ( [id] => 19392493 [patent_doc_number] => 20240282363 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-08-22 [patent_title] => VARIABLE READ METHOD FOR READ TIME PERFORMANCE IMPROVEMENT OF NON-VOLATILE MEMORY [patent_app_type] => utility [patent_app_number] => 18/225344 [patent_app_country] => US [patent_app_date] => 2023-07-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 18380 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18225344 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/225344
Variable read method for read time performance improvement of non-volatile memory Jul 23, 2023 Issued
Array ( [id] => 19145981 [patent_doc_number] => 20240144996 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-05-02 [patent_title] => FAST DIRECT LOOK AHEAD READ MODE IN A MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 18/356774 [patent_app_country] => US [patent_app_date] => 2023-07-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 18153 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 161 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18356774 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/356774
Fast direct look ahead read mode in a memory device Jul 20, 2023 Issued
Array ( [id] => 19406891 [patent_doc_number] => 20240290402 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-08-29 [patent_title] => INTERMEDIATE RE-VERIFY FOR ACHIEVING TIGHTER THRESHOLD VOLTAGE DISTRIBUTIONS IN A MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 18/223782 [patent_app_country] => US [patent_app_date] => 2023-07-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13162 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 188 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18223782 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/223782
Intermediate re-verify for achieving tighter threshold voltage distributions in a memory device Jul 18, 2023 Issued
Array ( [id] => 19406891 [patent_doc_number] => 20240290402 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-08-29 [patent_title] => INTERMEDIATE RE-VERIFY FOR ACHIEVING TIGHTER THRESHOLD VOLTAGE DISTRIBUTIONS IN A MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 18/223782 [patent_app_country] => US [patent_app_date] => 2023-07-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13162 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 188 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18223782 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/223782
Intermediate re-verify for achieving tighter threshold voltage distributions in a memory device Jul 18, 2023 Issued
Array ( [id] => 19205872 [patent_doc_number] => 20240177771 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-05-30 [patent_title] => SELF-SELECTING MEMORY DEVICE, MEMORY SYSTEM HAVING THE SAME, AND OPERATING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 18/334790 [patent_app_country] => US [patent_app_date] => 2023-06-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6364 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18334790 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/334790
Self-selecting memory device, memory system having the same, and operating method thereof Jun 13, 2023 Issued
Array ( [id] => 19205872 [patent_doc_number] => 20240177771 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-05-30 [patent_title] => SELF-SELECTING MEMORY DEVICE, MEMORY SYSTEM HAVING THE SAME, AND OPERATING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 18/334790 [patent_app_country] => US [patent_app_date] => 2023-06-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6364 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18334790 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/334790
Self-selecting memory device, memory system having the same, and operating method thereof Jun 13, 2023 Issued
Array ( [id] => 19633014 [patent_doc_number] => 20240411463 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-12-12 [patent_title] => QUEUED CURRENT LEVEL ADJUSTMENT IN A FLASH MEMORY SYSTEM [patent_app_type] => utility [patent_app_number] => 18/331612 [patent_app_country] => US [patent_app_date] => 2023-06-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 17667 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -26 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18331612 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/331612
QUEUED CURRENT LEVEL ADJUSTMENT IN A FLASH MEMORY SYSTEM Jun 7, 2023 Pending
Array ( [id] => 19633014 [patent_doc_number] => 20240411463 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-12-12 [patent_title] => QUEUED CURRENT LEVEL ADJUSTMENT IN A FLASH MEMORY SYSTEM [patent_app_type] => utility [patent_app_number] => 18/331612 [patent_app_country] => US [patent_app_date] => 2023-06-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 17667 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -26 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18331612 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/331612
QUEUED CURRENT LEVEL ADJUSTMENT IN A FLASH MEMORY SYSTEM Jun 7, 2023 Pending
Array ( [id] => 20375065 [patent_doc_number] => 12482507 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-11-25 [patent_title] => Memory device configured to generate read current based on size of memory cell and value of read current actually applied to memory cell [patent_app_type] => utility [patent_app_number] => 18/329215 [patent_app_country] => US [patent_app_date] => 2023-06-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 23 [patent_no_of_words] => 8498 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 190 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18329215 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/329215
Memory device configured to generate read current based on size of memory cell and value of read current actually applied to memory cell Jun 4, 2023 Issued
Array ( [id] => 18652812 [patent_doc_number] => 20230298652 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-09-21 [patent_title] => MEMORY DEVICE HAVING 2-TRANSISTOR VERTICAL MEMORY CELL AND SHIELD STRUCTURES [patent_app_type] => utility [patent_app_number] => 18/200871 [patent_app_country] => US [patent_app_date] => 2023-05-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16842 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 185 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18200871 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/200871
Memory device having 2-transistor vertical memory cell and shield structures May 22, 2023 Issued
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