Search

Douglas King

Examiner (ID: 15404, Phone: (571)272-2311 , Office: P/2824 )

Most Active Art Unit
2824
Art Unit(s)
2824
Total Applications
1004
Issued Applications
774
Pending Applications
71
Abandoned Applications
171

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 19559652 [patent_doc_number] => 20240371444 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-11-07 [patent_title] => ASYMMETRIC VREADK TO REDUCE NEIGHBORING WORD LINE INTERFERENCE IN A MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 18/228795 [patent_app_country] => US [patent_app_date] => 2023-08-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14307 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18228795 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/228795
Asymmetric VREADK to reduce neighboring word line interference in a memory device Jul 31, 2023 Issued
Array ( [id] => 18925250 [patent_doc_number] => 20240028254 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-01-25 [patent_title] => COMPUTING-IN-MEMORY DEVICE AND METHOD [patent_app_type] => utility [patent_app_number] => 18/362667 [patent_app_country] => US [patent_app_date] => 2023-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3614 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18362667 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/362667
Computing-in-memory device and method Jul 30, 2023 Issued
Array ( [id] => 20648189 [patent_doc_number] => 12603139 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-04-14 [patent_title] => Non-volatile memory with high performance read [patent_app_type] => utility [patent_app_number] => 18/362509 [patent_app_country] => US [patent_app_date] => 2023-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 30 [patent_no_of_words] => 18347 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 153 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18362509 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/362509
Non-volatile memory with high performance read Jul 30, 2023 Issued
Array ( [id] => 20455761 [patent_doc_number] => 12518821 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-01-06 [patent_title] => Pseudo multi-port memory with memory cells each having two-port memory cell architecture and multiple enable pulses on same wordline and associated memory access method [patent_app_type] => utility [patent_app_number] => 18/228621 [patent_app_country] => US [patent_app_date] => 2023-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 0 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 230 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18228621 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/228621
Pseudo multi-port memory with memory cells each having two-port memory cell architecture and multiple enable pulses on same wordline and associated memory access method Jul 30, 2023 Issued
Array ( [id] => 19628737 [patent_doc_number] => 12167613 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-12-10 [patent_title] => Circuit and method to enhance efficiency of memory [patent_app_type] => utility [patent_app_number] => 18/361897 [patent_app_country] => US [patent_app_date] => 2023-07-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6339 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18361897 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/361897
Circuit and method to enhance efficiency of memory Jul 29, 2023 Issued
Array ( [id] => 19618902 [patent_doc_number] => 20240404582 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-12-05 [patent_title] => MEMORY CONTROLLER SUPPORT FOR MIXED READ [patent_app_type] => utility [patent_app_number] => 18/360096 [patent_app_country] => US [patent_app_date] => 2023-07-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13151 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18360096 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/360096
Memory controller support for mixed read Jul 26, 2023 Issued
Array ( [id] => 19392493 [patent_doc_number] => 20240282363 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-08-22 [patent_title] => VARIABLE READ METHOD FOR READ TIME PERFORMANCE IMPROVEMENT OF NON-VOLATILE MEMORY [patent_app_type] => utility [patent_app_number] => 18/225344 [patent_app_country] => US [patent_app_date] => 2023-07-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 18380 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18225344 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/225344
Variable read method for read time performance improvement of non-volatile memory Jul 23, 2023 Issued
Array ( [id] => 19145981 [patent_doc_number] => 20240144996 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-05-02 [patent_title] => FAST DIRECT LOOK AHEAD READ MODE IN A MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 18/356774 [patent_app_country] => US [patent_app_date] => 2023-07-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 18153 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 161 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18356774 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/356774
Fast direct look ahead read mode in a memory device Jul 20, 2023 Issued
Array ( [id] => 19406891 [patent_doc_number] => 20240290402 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-08-29 [patent_title] => INTERMEDIATE RE-VERIFY FOR ACHIEVING TIGHTER THRESHOLD VOLTAGE DISTRIBUTIONS IN A MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 18/223782 [patent_app_country] => US [patent_app_date] => 2023-07-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13162 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 188 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18223782 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/223782
Intermediate re-verify for achieving tighter threshold voltage distributions in a memory device Jul 18, 2023 Issued
Array ( [id] => 19205872 [patent_doc_number] => 20240177771 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-05-30 [patent_title] => SELF-SELECTING MEMORY DEVICE, MEMORY SYSTEM HAVING THE SAME, AND OPERATING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 18/334790 [patent_app_country] => US [patent_app_date] => 2023-06-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6364 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18334790 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/334790
Self-selecting memory device, memory system having the same, and operating method thereof Jun 13, 2023 Issued
Array ( [id] => 19633014 [patent_doc_number] => 20240411463 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-12-12 [patent_title] => QUEUED CURRENT LEVEL ADJUSTMENT IN A FLASH MEMORY SYSTEM [patent_app_type] => utility [patent_app_number] => 18/331612 [patent_app_country] => US [patent_app_date] => 2023-06-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 17667 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -26 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18331612 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/331612
QUEUED CURRENT LEVEL ADJUSTMENT IN A FLASH MEMORY SYSTEM Jun 7, 2023 Abandoned
Array ( [id] => 20375065 [patent_doc_number] => 12482507 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-11-25 [patent_title] => Memory device configured to generate read current based on size of memory cell and value of read current actually applied to memory cell [patent_app_type] => utility [patent_app_number] => 18/329215 [patent_app_country] => US [patent_app_date] => 2023-06-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 23 [patent_no_of_words] => 8498 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 190 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18329215 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/329215
Memory device configured to generate read current based on size of memory cell and value of read current actually applied to memory cell Jun 4, 2023 Issued
Array ( [id] => 18652812 [patent_doc_number] => 20230298652 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-09-21 [patent_title] => MEMORY DEVICE HAVING 2-TRANSISTOR VERTICAL MEMORY CELL AND SHIELD STRUCTURES [patent_app_type] => utility [patent_app_number] => 18/200871 [patent_app_country] => US [patent_app_date] => 2023-05-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16842 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 185 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18200871 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/200871
Memory device having 2-transistor vertical memory cell and shield structures May 22, 2023 Issued
Array ( [id] => 19980030 [patent_doc_number] => 12347516 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-07-01 [patent_title] => Random access memory and sense-amplifying compensation circuit thereof [patent_app_type] => utility [patent_app_number] => 18/197106 [patent_app_country] => US [patent_app_date] => 2023-05-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 14 [patent_no_of_words] => 7623 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 259 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18197106 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/197106
Random access memory and sense-amplifying compensation circuit thereof May 14, 2023 Issued
Array ( [id] => 18659746 [patent_doc_number] => 20230305753 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-09-28 [patent_title] => MEMORY SYSTEM AND SHIFT REGISTER MEMORY [patent_app_type] => utility [patent_app_number] => 18/309038 [patent_app_country] => US [patent_app_date] => 2023-04-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 26071 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -10 [patent_words_short_claim] => 156 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18309038 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/309038
Memory system and shift register memory Apr 27, 2023 Issued
Array ( [id] => 18570248 [patent_doc_number] => 20230260585 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-08-17 [patent_title] => POWER CIRCUIT AND METHOD FOR PROVIDING POWER TO ELECTRONIC FUSE CIRCUIT [patent_app_type] => utility [patent_app_number] => 18/306221 [patent_app_country] => US [patent_app_date] => 2023-04-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5170 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 179 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18306221 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/306221
Electronic fuse circuit and method for electronic fuse circuit Apr 23, 2023 Issued
Array ( [id] => 19347183 [patent_doc_number] => 20240256146 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-08-01 [patent_title] => REDUNDANCY FOR AN ARRAY OF NON-VOLATILE MEMORY CELLS USING TAG REGISTERS [patent_app_type] => utility [patent_app_number] => 18/134928 [patent_app_country] => US [patent_app_date] => 2023-04-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13818 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 50 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18134928 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/134928
Redundancy for an array of non-volatile memory cells using tag registers Apr 13, 2023 Issued
Array ( [id] => 19347183 [patent_doc_number] => 20240256146 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-08-01 [patent_title] => REDUNDANCY FOR AN ARRAY OF NON-VOLATILE MEMORY CELLS USING TAG REGISTERS [patent_app_type] => utility [patent_app_number] => 18/134928 [patent_app_country] => US [patent_app_date] => 2023-04-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13818 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 50 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18134928 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/134928
Redundancy for an array of non-volatile memory cells using tag registers Apr 13, 2023 Issued
Array ( [id] => 19347183 [patent_doc_number] => 20240256146 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-08-01 [patent_title] => REDUNDANCY FOR AN ARRAY OF NON-VOLATILE MEMORY CELLS USING TAG REGISTERS [patent_app_type] => utility [patent_app_number] => 18/134928 [patent_app_country] => US [patent_app_date] => 2023-04-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13818 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 50 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18134928 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/134928
Redundancy for an array of non-volatile memory cells using tag registers Apr 13, 2023 Issued
Array ( [id] => 19347183 [patent_doc_number] => 20240256146 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-08-01 [patent_title] => REDUNDANCY FOR AN ARRAY OF NON-VOLATILE MEMORY CELLS USING TAG REGISTERS [patent_app_type] => utility [patent_app_number] => 18/134928 [patent_app_country] => US [patent_app_date] => 2023-04-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13818 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 50 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18134928 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/134928
Redundancy for an array of non-volatile memory cells using tag registers Apr 13, 2023 Issued
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