Search

Douglas King

Examiner (ID: 126, Phone: (571)272-2311 , Office: P/2824 )

Most Active Art Unit
2824
Art Unit(s)
2824
Total Applications
970
Issued Applications
746
Pending Applications
78
Abandoned Applications
170

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 18848517 [patent_doc_number] => 20230410921 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-12-21 [patent_title] => THREE-BIT-PER-CELL PROGRAMMING USING A FOUR-BIT-PER-CELL PROGRAMMING ALGORITHM [patent_app_type] => utility [patent_app_number] => 17/845060 [patent_app_country] => US [patent_app_date] => 2022-06-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14609 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 54 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17845060 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/845060
Three-bit-per-cell programming using a four-bit-per-cell programming algorithm Jun 20, 2022 Issued
Array ( [id] => 18148225 [patent_doc_number] => 20230022082 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-01-26 [patent_title] => SEMICONDUCTOR MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 17/806965 [patent_app_country] => US [patent_app_date] => 2022-06-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 25812 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 29 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17806965 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/806965
Semiconductor memory device Jun 14, 2022 Issued
Array ( [id] => 17900509 [patent_doc_number] => 20220310171 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-09-29 [patent_title] => ERASE METHOD OF NON-VOLATILE MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 17/840021 [patent_app_country] => US [patent_app_date] => 2022-06-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9612 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 182 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17840021 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/840021
Erase method of non-volatile memory device Jun 13, 2022 Issued
Array ( [id] => 18623578 [patent_doc_number] => 11756631 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-09-12 [patent_title] => Adjusting read voltage levels based on a programmed bit count in a memory sub-system [patent_app_type] => utility [patent_app_number] => 17/838594 [patent_app_country] => US [patent_app_date] => 2022-06-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6522 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17838594 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/838594
Adjusting read voltage levels based on a programmed bit count in a memory sub-system Jun 12, 2022 Issued
Array ( [id] => 20243933 [patent_doc_number] => 12424263 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-09-23 [patent_title] => Apparatuses and methods for arranging read data for output [patent_app_type] => utility [patent_app_number] => 17/827582 [patent_app_country] => US [patent_app_date] => 2022-05-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 11 [patent_no_of_words] => 4672 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17827582 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/827582
Apparatuses and methods for arranging read data for output May 26, 2022 Issued
Array ( [id] => 18039720 [patent_doc_number] => 20220383937 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-12-01 [patent_title] => MEMORY DEVICE AND METHOD FOR PERFORMING CONSECUTIVE MEMORY ACCESSES [patent_app_type] => utility [patent_app_number] => 17/746065 [patent_app_country] => US [patent_app_date] => 2022-05-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6148 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17746065 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/746065
Memory device and method for performing consecutive memory accesses May 16, 2022 Issued
Array ( [id] => 19795381 [patent_doc_number] => 12236332 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-02-25 [patent_title] => Compute-in-memory macro device and electronic device [patent_app_type] => utility [patent_app_number] => 17/743473 [patent_app_country] => US [patent_app_date] => 2022-05-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 3407 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 179 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17743473 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/743473
Compute-in-memory macro device and electronic device May 12, 2022 Issued
Array ( [id] => 19328634 [patent_doc_number] => 12046323 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-07-23 [patent_title] => Semiconductor device and semiconductor system [patent_app_type] => utility [patent_app_number] => 17/741099 [patent_app_country] => US [patent_app_date] => 2022-05-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 7926 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17741099 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/741099
Semiconductor device and semiconductor system May 9, 2022 Issued
Array ( [id] => 17833350 [patent_doc_number] => 20220270654 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-08-25 [patent_title] => APPARATUSES INCLUDING TEMPERATURE-BASED THRESHOLD VOLTAGE COMPENSATED SENSE AMPLIFIERS AND METHODS FOR COMPENSATING SAME [patent_app_type] => utility [patent_app_number] => 17/741092 [patent_app_country] => US [patent_app_date] => 2022-05-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7991 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 45 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17741092 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/741092
Apparatuses including temperature-based threshold voltage compensated sense amplifiers and methods for compensating same May 9, 2022 Issued
Array ( [id] => 17809789 [patent_doc_number] => 20220261624 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-08-18 [patent_title] => NEURAL NETWORK CIRCUITS HAVING NON-VOLATILE SYNAPSE ARRAYS [patent_app_type] => utility [patent_app_number] => 17/737342 [patent_app_country] => US [patent_app_date] => 2022-05-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9108 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -9 [patent_words_short_claim] => 223 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17737342 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/737342
Neural network circuits having non-volatile synapse arrays May 4, 2022 Issued
Array ( [id] => 18757242 [patent_doc_number] => 20230360700 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-11-09 [patent_title] => CROSS-POINT ARRAY WITH THRESHOLD SWITCHING SELECTOR MEMORY ELEMENT [patent_app_type] => utility [patent_app_number] => 17/735277 [patent_app_country] => US [patent_app_date] => 2022-05-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 19918 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 214 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17735277 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/735277
Cross-point array with threshold switching selector memory element May 2, 2022 Issued
Array ( [id] => 17984486 [patent_doc_number] => 20220350523 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-11-03 [patent_title] => STACK REGISTER HAVING DIFFERENT FERROELECTRIC MEMORY ELEMENT CONSTRUCTIONS [patent_app_type] => utility [patent_app_number] => 17/730345 [patent_app_country] => US [patent_app_date] => 2022-04-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4963 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17730345 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/730345
Stack register having different ferroelectric memory element constructions Apr 26, 2022 Issued
Array ( [id] => 19523775 [patent_doc_number] => 12125513 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-10-22 [patent_title] => System on chip (SOC) with processor and integrated ferroelectric memory [patent_app_type] => utility [patent_app_number] => 17/726864 [patent_app_country] => US [patent_app_date] => 2022-04-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 22 [patent_no_of_words] => 10096 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17726864 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/726864
System on chip (SOC) with processor and integrated ferroelectric memory Apr 21, 2022 Issued
Array ( [id] => 17779864 [patent_doc_number] => 20220246214 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-08-04 [patent_title] => One-Ladder Read of Memory Cells Coarsely Programmed via Interleaved Two-Pass Data Programming Techniques [patent_app_type] => utility [patent_app_number] => 17/724940 [patent_app_country] => US [patent_app_date] => 2022-04-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 17500 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 160 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17724940 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/724940
One-ladder read of memory cells coarsely programmed via interleaved two-pass data programming techniques Apr 19, 2022 Issued
Array ( [id] => 19459955 [patent_doc_number] => 12100457 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-09-24 [patent_title] => Voltage supply circuits, three-dimensional memory devices, peripheral circuit, and methods for adjusting voltage supply circuit [patent_app_type] => utility [patent_app_number] => 17/725109 [patent_app_country] => US [patent_app_date] => 2022-04-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 11 [patent_no_of_words] => 8176 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17725109 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/725109
Voltage supply circuits, three-dimensional memory devices, peripheral circuit, and methods for adjusting voltage supply circuit Apr 19, 2022 Issued
Array ( [id] => 18735536 [patent_doc_number] => 11804277 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-10-31 [patent_title] => Error remapping [patent_app_type] => utility [patent_app_number] => 17/722667 [patent_app_country] => US [patent_app_date] => 2022-04-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 3908 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 159 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17722667 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/722667
Error remapping Apr 17, 2022 Issued
Array ( [id] => 19237040 [patent_doc_number] => 20240194235 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-06-13 [patent_title] => MAGNETIC MEMORY ELEMENT [patent_app_type] => utility [patent_app_number] => 18/286434 [patent_app_country] => US [patent_app_date] => 2022-04-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6327 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -7 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18286434 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/286434
MAGNETIC MEMORY ELEMENT Apr 11, 2022 Pending
Array ( [id] => 17932959 [patent_doc_number] => 20220328085 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-10-13 [patent_title] => MEMORY DEVICE WHICH GENERATES IMPROVED READ CURRENT ACCORDING TO SIZE OF MEMORY CELL [patent_app_type] => utility [patent_app_number] => 17/709784 [patent_app_country] => US [patent_app_date] => 2022-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12324 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17709784 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/709784
Memory device which generates improved read current according to size of memory cell Mar 30, 2022 Issued
Array ( [id] => 19733535 [patent_doc_number] => 12211535 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-01-28 [patent_title] => Magnetoresistive memory device and method of operating same using ferroelectric-controlled exchange coupling [patent_app_type] => utility [patent_app_number] => 17/656310 [patent_app_country] => US [patent_app_date] => 2022-03-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 9294 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17656310 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/656310
Magnetoresistive memory device and method of operating same using ferroelectric-controlled exchange coupling Mar 23, 2022 Issued
Array ( [id] => 18660237 [patent_doc_number] => 20230306245 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-09-28 [patent_title] => PROGRAMMING CIRCUIT, INTEGRATED CIRCUIT, AND METHOD [patent_app_type] => utility [patent_app_number] => 17/703889 [patent_app_country] => US [patent_app_date] => 2022-03-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13584 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17703889 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/703889
PROGRAMMING CIRCUIT, INTEGRATED CIRCUIT, AND METHOD Mar 23, 2022 Pending
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