Douglas King

Array ( [id] => 18857065 [patent_doc_number] => 11854656 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-12-26 [patent_title] => Memory refresh [patent_app_type] => utility [patent_app_number] => 17/817898 [patent_app_country] => US [patent_app_date] => 2022-08-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 8093 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 56 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17817898 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18958661 [patent_doc_number] => 20240046988 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-02-08 [patent_title] => DIFFERENTIABLE CONTENT ADDRESSABLE MEMORY [patent_app_type] => utility [patent_app_number] => 17/876471 [patent_app_country] => US [patent_app_date] => 2022-07-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 19023 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17876471 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18514397 [patent_doc_number] => 20230230652 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-07-20 [patent_title] => TESTING SYSTEM AND TESTING METHOD [patent_app_type] => utility [patent_app_number] => 17/814232 [patent_app_country] => US [patent_app_date] => 2022-07-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3304 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 57 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17814232 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19244337 [patent_doc_number] => 12014788 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-06-18 [patent_title] => Memory array detection circuit and detection method, and memory [patent_app_type] => utility [patent_app_number] => 17/813597 [patent_app_country] => US [patent_app_date] => 2022-07-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 7206 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 358 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17813597 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18820790 [patent_doc_number] => 20230395131 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-12-07 [patent_title] => Sense Amplifier Reference Voltage Through Sense Amplifier Latch Devices [patent_app_type] => utility [patent_app_number] => 17/860470 [patent_app_country] => US [patent_app_date] => 2022-07-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6235 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -20 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17860470 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19703707 [patent_doc_number] => 12197742 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-01-14 [patent_title] => Managing error compensation using charge coupling and lateral migration sensitivity [patent_app_type] => utility [patent_app_number] => 17/860701 [patent_app_country] => US [patent_app_date] => 2022-07-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 15596 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17860701 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18222457 [patent_doc_number] => 20230061451 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-03-02 [patent_title] => ZIGZAG WIRED MEMORY MODULE [patent_app_type] => utility [patent_app_number] => 17/852556 [patent_app_country] => US [patent_app_date] => 2022-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10958 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 158 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17852556 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18144568 [patent_doc_number] => 20230018420 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-01-19 [patent_title] => SRAM WITH FAST, CONTROLLED PEAK CURRENT, POWER EFFICIENT ARRAY RESET, AND DATA CORRUPTION MODES FOR SECURE APPLICATIONS [patent_app_type] => utility [patent_app_number] => 17/853026 [patent_app_country] => US [patent_app_date] => 2022-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9265 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17853026 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18364090 [patent_doc_number] => 20230145681 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-05-11 [patent_title] => METHOD OF PROGRAMMING NON-VOLATILE MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 17/852057 [patent_app_country] => US [patent_app_date] => 2022-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14392 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17852057 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18865624 [patent_doc_number] => 20230420061 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-12-28 [patent_title] => NON-VOLATILE MEMORY WITH PRECISE PROGRAMMING [patent_app_type] => utility [patent_app_number] => 17/852129 [patent_app_country] => US [patent_app_date] => 2022-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 21810 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 168 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17852129 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20305205 [patent_doc_number] => 12451201 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-10-21 [patent_title] => Hybrid precharge select scheme to save program ICC [patent_app_type] => utility [patent_app_number] => 17/845318 [patent_app_country] => US [patent_app_date] => 2022-06-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 27 [patent_no_of_words] => 7189 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 176 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17845318 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18848517 [patent_doc_number] => 20230410921 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-12-21 [patent_title] => THREE-BIT-PER-CELL PROGRAMMING USING A FOUR-BIT-PER-CELL PROGRAMMING ALGORITHM [patent_app_type] => utility [patent_app_number] => 17/845060 [patent_app_country] => US [patent_app_date] => 2022-06-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14609 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 54 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17845060 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18848452 [patent_doc_number] => 20230410856 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-12-21 [patent_title] => MEMORY CHIP, MEMORY DEVICE AND OPERATION METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 17/845008 [patent_app_country] => US [patent_app_date] => 2022-06-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4810 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 205 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17845008 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18148225 [patent_doc_number] => 20230022082 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-01-26 [patent_title] => SEMICONDUCTOR MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 17/806965 [patent_app_country] => US [patent_app_date] => 2022-06-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 25812 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 29 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17806965 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17900509 [patent_doc_number] => 20220310171 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-09-29 [patent_title] => ERASE METHOD OF NON-VOLATILE MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 17/840021 [patent_app_country] => US [patent_app_date] => 2022-06-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9612 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 182 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17840021 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18623578 [patent_doc_number] => 11756631 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-09-12 [patent_title] => Adjusting read voltage levels based on a programmed bit count in a memory sub-system [patent_app_type] => utility [patent_app_number] => 17/838594 [patent_app_country] => US [patent_app_date] => 2022-06-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6522 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17838594 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20243933 [patent_doc_number] => 12424263 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-09-23 [patent_title] => Apparatuses and methods for arranging read data for output [patent_app_type] => utility [patent_app_number] => 17/827582 [patent_app_country] => US [patent_app_date] => 2022-05-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 11 [patent_no_of_words] => 4672 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17827582 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18039720 [patent_doc_number] => 20220383937 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-12-01 [patent_title] => MEMORY DEVICE AND METHOD FOR PERFORMING CONSECUTIVE MEMORY ACCESSES [patent_app_type] => utility [patent_app_number] => 17/746065 [patent_app_country] => US [patent_app_date] => 2022-05-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6148 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17746065 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19795381 [patent_doc_number] => 12236332 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-02-25 [patent_title] => Compute-in-memory macro device and electronic device [patent_app_type] => utility [patent_app_number] => 17/743473 [patent_app_country] => US [patent_app_date] => 2022-05-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 3407 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 179 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17743473 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17833350 [patent_doc_number] => 20220270654 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-08-25 [patent_title] => APPARATUSES INCLUDING TEMPERATURE-BASED THRESHOLD VOLTAGE COMPENSATED SENSE AMPLIFIERS AND METHODS FOR COMPENSATING SAME [patent_app_type] => utility [patent_app_number] => 17/741092 [patent_app_country] => US [patent_app_date] => 2022-05-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7991 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 45 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17741092 [rel_patent_id] =>[rel_patent_doc_number] =>)