Search

Douglas King

Examiner (ID: 15404, Phone: (571)272-2311 , Office: P/2824 )

Most Active Art Unit
2824
Art Unit(s)
2824
Total Applications
1004
Issued Applications
774
Pending Applications
71
Abandoned Applications
171

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 19328634 [patent_doc_number] => 12046323 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-07-23 [patent_title] => Semiconductor device and semiconductor system [patent_app_type] => utility [patent_app_number] => 17/741099 [patent_app_country] => US [patent_app_date] => 2022-05-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 7926 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17741099 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/741099
Semiconductor device and semiconductor system May 9, 2022 Issued
Array ( [id] => 17809789 [patent_doc_number] => 20220261624 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-08-18 [patent_title] => NEURAL NETWORK CIRCUITS HAVING NON-VOLATILE SYNAPSE ARRAYS [patent_app_type] => utility [patent_app_number] => 17/737342 [patent_app_country] => US [patent_app_date] => 2022-05-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9108 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -9 [patent_words_short_claim] => 223 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17737342 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/737342
Neural network circuits having non-volatile synapse arrays May 4, 2022 Issued
Array ( [id] => 18757242 [patent_doc_number] => 20230360700 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-11-09 [patent_title] => CROSS-POINT ARRAY WITH THRESHOLD SWITCHING SELECTOR MEMORY ELEMENT [patent_app_type] => utility [patent_app_number] => 17/735277 [patent_app_country] => US [patent_app_date] => 2022-05-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 19918 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 214 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17735277 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/735277
Cross-point array with threshold switching selector memory element May 2, 2022 Issued
Array ( [id] => 17984486 [patent_doc_number] => 20220350523 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-11-03 [patent_title] => STACK REGISTER HAVING DIFFERENT FERROELECTRIC MEMORY ELEMENT CONSTRUCTIONS [patent_app_type] => utility [patent_app_number] => 17/730345 [patent_app_country] => US [patent_app_date] => 2022-04-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4963 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17730345 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/730345
Stack register having different ferroelectric memory element constructions Apr 26, 2022 Issued
Array ( [id] => 19523775 [patent_doc_number] => 12125513 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-10-22 [patent_title] => System on chip (SOC) with processor and integrated ferroelectric memory [patent_app_type] => utility [patent_app_number] => 17/726864 [patent_app_country] => US [patent_app_date] => 2022-04-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 22 [patent_no_of_words] => 10096 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17726864 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/726864
System on chip (SOC) with processor and integrated ferroelectric memory Apr 21, 2022 Issued
Array ( [id] => 19459955 [patent_doc_number] => 12100457 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-09-24 [patent_title] => Voltage supply circuits, three-dimensional memory devices, peripheral circuit, and methods for adjusting voltage supply circuit [patent_app_type] => utility [patent_app_number] => 17/725109 [patent_app_country] => US [patent_app_date] => 2022-04-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 11 [patent_no_of_words] => 8176 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17725109 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/725109
Voltage supply circuits, three-dimensional memory devices, peripheral circuit, and methods for adjusting voltage supply circuit Apr 19, 2022 Issued
Array ( [id] => 17779864 [patent_doc_number] => 20220246214 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-08-04 [patent_title] => One-Ladder Read of Memory Cells Coarsely Programmed via Interleaved Two-Pass Data Programming Techniques [patent_app_type] => utility [patent_app_number] => 17/724940 [patent_app_country] => US [patent_app_date] => 2022-04-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 17500 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 160 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17724940 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/724940
One-ladder read of memory cells coarsely programmed via interleaved two-pass data programming techniques Apr 19, 2022 Issued
Array ( [id] => 18735536 [patent_doc_number] => 11804277 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-10-31 [patent_title] => Error remapping [patent_app_type] => utility [patent_app_number] => 17/722667 [patent_app_country] => US [patent_app_date] => 2022-04-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 3908 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 159 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17722667 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/722667
Error remapping Apr 17, 2022 Issued
Array ( [id] => 20718073 [patent_doc_number] => 12633329 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-05-19 [patent_title] => Magnetic memory element [patent_app_type] => utility [patent_app_number] => 18/286434 [patent_app_country] => US [patent_app_date] => 2022-04-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 20 [patent_no_of_words] => 1926 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18286434 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/286434
Magnetic memory element Apr 11, 2022 Issued
Array ( [id] => 17932959 [patent_doc_number] => 20220328085 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-10-13 [patent_title] => MEMORY DEVICE WHICH GENERATES IMPROVED READ CURRENT ACCORDING TO SIZE OF MEMORY CELL [patent_app_type] => utility [patent_app_number] => 17/709784 [patent_app_country] => US [patent_app_date] => 2022-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12324 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17709784 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/709784
Memory device which generates improved read current according to size of memory cell Mar 30, 2022 Issued
Array ( [id] => 18660237 [patent_doc_number] => 20230306245 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-09-28 [patent_title] => PROGRAMMING CIRCUIT, INTEGRATED CIRCUIT, AND METHOD [patent_app_type] => utility [patent_app_number] => 17/703889 [patent_app_country] => US [patent_app_date] => 2022-03-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13584 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17703889 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/703889
PROGRAMMING CIRCUIT, INTEGRATED CIRCUIT, AND METHOD Mar 23, 2022 Pending
Array ( [id] => 19160086 [patent_doc_number] => 20240152793 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-05-09 [patent_title] => INFORMATION PROCESSING APPARATUS [patent_app_type] => utility [patent_app_number] => 18/550827 [patent_app_country] => US [patent_app_date] => 2022-03-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7034 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -21 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18550827 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/550827
INFORMATION PROCESSING APPARATUS Mar 23, 2022 Pending
Array ( [id] => 19733535 [patent_doc_number] => 12211535 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-01-28 [patent_title] => Magnetoresistive memory device and method of operating same using ferroelectric-controlled exchange coupling [patent_app_type] => utility [patent_app_number] => 17/656310 [patent_app_country] => US [patent_app_date] => 2022-03-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 9294 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17656310 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/656310
Magnetoresistive memory device and method of operating same using ferroelectric-controlled exchange coupling Mar 23, 2022 Issued
Array ( [id] => 18652811 [patent_doc_number] => 20230298651 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-09-21 [patent_title] => DATA PROCESSING METHOD, DATA PROCESSING CIRCUIT, AND COMPUTING APPARATUS [patent_app_type] => utility [patent_app_number] => 17/697951 [patent_app_country] => US [patent_app_date] => 2022-03-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3974 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 54 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17697951 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/697951
Data processing method, data processing circuit, and computing apparatus Mar 17, 2022 Issued
Array ( [id] => 19259842 [patent_doc_number] => 12019900 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-06-25 [patent_title] => Temperature-based memory management [patent_app_type] => utility [patent_app_number] => 17/697509 [patent_app_country] => US [patent_app_date] => 2022-03-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 22702 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17697509 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/697509
Temperature-based memory management Mar 16, 2022 Issued
Array ( [id] => 19046476 [patent_doc_number] => 11935595 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-03-19 [patent_title] => Flash memory device, controller, and method capable of performing access operation upon data unit(s) of multiple planes of flash memory device in response one simplified command sequence [patent_app_type] => utility [patent_app_number] => 17/679125 [patent_app_country] => US [patent_app_date] => 2022-02-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 32 [patent_figures_cnt] => 35 [patent_no_of_words] => 24962 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 294 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17679125 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/679125
Flash memory device, controller, and method capable of performing access operation upon data unit(s) of multiple planes of flash memory device in response one simplified command sequence Feb 23, 2022 Issued
Array ( [id] => 18270142 [patent_doc_number] => 20230091384 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-03-23 [patent_title] => MEMORY SYSTEM AND CONTROL METHOD OF MEMORY SYSTEM [patent_app_type] => utility [patent_app_number] => 17/651309 [patent_app_country] => US [patent_app_date] => 2022-02-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9782 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 146 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17651309 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/651309
Memory system and control method of memory system Feb 15, 2022 Issued
Array ( [id] => 18578708 [patent_doc_number] => 11735247 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-08-22 [patent_title] => Semiconductor device with word line degradation monitor and associated methods and systems [patent_app_type] => utility [patent_app_number] => 17/672537 [patent_app_country] => US [patent_app_date] => 2022-02-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 12899 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17672537 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/672537
Semiconductor device with word line degradation monitor and associated methods and systems Feb 14, 2022 Issued
Array ( [id] => 18415839 [patent_doc_number] => 11670384 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-06-06 [patent_title] => Memory system capable of reducing the reading time [patent_app_type] => utility [patent_app_number] => 17/587998 [patent_app_country] => US [patent_app_date] => 2022-01-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 3748 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17587998 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/587998
Memory system capable of reducing the reading time Jan 27, 2022 Issued
Array ( [id] => 17737725 [patent_doc_number] => 20220223187 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-07-14 [patent_title] => TECHNIQUES FOR PRECHARGING A MEMORY CELL [patent_app_type] => utility [patent_app_number] => 17/585307 [patent_app_country] => US [patent_app_date] => 2022-01-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 17468 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17585307 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/585307
Techniques for precharging a memory cell Jan 25, 2022 Issued
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