Search

Dov Popovici

Examiner (ID: 14019, Phone: (571)272-4083 , Office: P/2677 )

Most Active Art Unit
2677
Art Unit(s)
2622, 2683, 2625, 2673, 2616, 2415, 2722, 2182, 2677, 2612
Total Applications
1258
Issued Applications
1089
Pending Applications
59
Abandoned Applications
110

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 7613832 [patent_doc_number] => 06898699 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-05-24 [patent_title] => 'Return address stack including speculative return address buffer with back pointers' [patent_app_type] => utility [patent_app_number] => 10/029128 [patent_app_country] => US [patent_app_date] => 2001-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 14 [patent_no_of_words] => 3699 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/898/06898699.pdf [firstpage_image] =>[orig_patent_app_number] => 10029128 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/029128
Return address stack including speculative return address buffer with back pointers Dec 20, 2001 Issued
Array ( [id] => 6484112 [patent_doc_number] => 20020023202 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-02-21 [patent_title] => 'Load value queue input replication in a simultaneous and redundantly threaded processor' [patent_app_type] => new [patent_app_number] => 09/839624 [patent_app_country] => US [patent_app_date] => 2001-04-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 6051 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0023/20020023202.pdf [firstpage_image] =>[orig_patent_app_number] => 09839624 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/839624
Load value queue input replication in a simultaneous and redundantly threaded processor Apr 18, 2001 Abandoned
Array ( [id] => 7626822 [patent_doc_number] => 06807622 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-10-19 [patent_title] => 'Processor which overrides default operand size for implicit stack pointer references and near branches' [patent_app_type] => B1 [patent_app_number] => 09/824992 [patent_app_country] => US [patent_app_date] => 2001-04-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 13 [patent_no_of_words] => 13009 [patent_no_of_claims] => 49 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 4 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/807/06807622.pdf [firstpage_image] =>[orig_patent_app_number] => 09824992 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/824992
Processor which overrides default operand size for implicit stack pointer references and near branches Apr 1, 2001 Issued
Array ( [id] => 1024910 [patent_doc_number] => 06889312 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-05-03 [patent_title] => 'Selective zero extension based on operand size' [patent_app_type] => utility [patent_app_number] => 09/824869 [patent_app_country] => US [patent_app_date] => 2001-04-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 17 [patent_no_of_words] => 13531 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/889/06889312.pdf [firstpage_image] =>[orig_patent_app_number] => 09824869 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/824869
Selective zero extension based on operand size Apr 1, 2001 Issued
Array ( [id] => 992702 [patent_doc_number] => 06920547 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-07-19 [patent_title] => 'Register adjustment based on adjustment values determined at multiple stages within a pipeline of a processor' [patent_app_type] => utility [patent_app_number] => 09/742745 [patent_app_country] => US [patent_app_date] => 2000-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 3698 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 60 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/920/06920547.pdf [firstpage_image] =>[orig_patent_app_number] => 09742745 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/742745
Register adjustment based on adjustment values determined at multiple stages within a pipeline of a processor Dec 19, 2000 Issued
Array ( [id] => 1100424 [patent_doc_number] => 06823448 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-11-23 [patent_title] => 'Exception handling using an exception pipeline in a pipelined processor' [patent_app_type] => B2 [patent_app_number] => 09/738081 [patent_app_country] => US [patent_app_date] => 2000-12-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 1840 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/823/06823448.pdf [firstpage_image] =>[orig_patent_app_number] => 09738081 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/738081
Exception handling using an exception pipeline in a pipelined processor Dec 14, 2000 Issued
Array ( [id] => 6283212 [patent_doc_number] => 20020108026 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-08-08 [patent_title] => 'Data processing apparatus with register file bypass' [patent_app_type] => new [patent_app_number] => 09/733597 [patent_app_country] => US [patent_app_date] => 2000-12-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 11747 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 381 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0108/20020108026.pdf [firstpage_image] =>[orig_patent_app_number] => 09733597 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/733597
Data processing apparatus with register file bypass Dec 7, 2000 Issued
09/710699 Method and apparatus for reducing branch latency Nov 9, 2000 Abandoned
Menu