Duc T. Doan

Array ( [id] => 68852 [patent_doc_number] => 07761650 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-07-20 [patent_title] => 'Processing wrong side I/O commands' [patent_app_type] => utility [patent_app_number] => 11/772175 [patent_app_country] => US [patent_app_date] => 2007-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 11 [patent_no_of_words] => 8536 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 176 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/761/07761650.pdf [firstpage_image] =>[orig_patent_app_number] => 11772175 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4576355 [patent_doc_number] => 07822915 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-10-26 [patent_title] => 'Memory controller for packet applications' [patent_app_type] => utility [patent_app_number] => 11/772135 [patent_app_country] => US [patent_app_date] => 2007-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 15 [patent_no_of_words] => 9690 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/822/07822915.pdf [firstpage_image] =>[orig_patent_app_number] => 11772135 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5351371 [patent_doc_number] => 20090006732 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-01-01 [patent_title] => 'STORAGE SYSTEM WITH SYNCHRONIZED PROCESSING ELEMENTS' [patent_app_type] => utility [patent_app_number] => 11/772139 [patent_app_country] => US [patent_app_date] => 2007-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 7604 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0006/20090006732.pdf [firstpage_image] =>[orig_patent_app_number] => 11772139 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5351432 [patent_doc_number] => 20090006793 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-01-01 [patent_title] => 'Method And Apparatus To Enable Runtime Memory Migration With Operating System Assistance' [patent_app_type] => utility [patent_app_number] => 11/772158 [patent_app_country] => US [patent_app_date] => 2007-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 6257 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0006/20090006793.pdf [firstpage_image] =>[orig_patent_app_number] => 11772158 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8764 [patent_doc_number] => 07818535 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2010-10-19 [patent_title] => 'Implicit container per version set' [patent_app_type] => utility [patent_app_number] => 11/772154 [patent_app_country] => US [patent_app_date] => 2007-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 57 [patent_figures_cnt] => 64 [patent_no_of_words] => 22392 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/818/07818535.pdf [firstpage_image] =>[orig_patent_app_number] => 11772154 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4512422 [patent_doc_number] => 07921264 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-04-05 [patent_title] => 'Dual-mode memory chip for high capacity memory subsystem' [patent_app_type] => utility [patent_app_number] => 11/769011 [patent_app_country] => US [patent_app_date] => 2007-06-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 14723 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 391 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/921/07921264.pdf [firstpage_image] =>[orig_patent_app_number] => 11769011 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18857 [patent_doc_number] => 07809913 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-10-05 [patent_title] => 'Memory chip for high capacity memory subsystem supporting multiple speed bus' [patent_app_type] => utility [patent_app_number] => 11/769006 [patent_app_country] => US [patent_app_date] => 2007-06-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 14866 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 307 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/809/07809913.pdf [firstpage_image] =>[orig_patent_app_number] => 11769006 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5351413 [patent_doc_number] => 20090006774 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-01-01 [patent_title] => 'High Capacity Memory Subsystem Architecture Employing Multiple-Speed Bus' [patent_app_type] => utility [patent_app_number] => 11/768998 [patent_app_country] => US [patent_app_date] => 2007-06-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 14894 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0006/20090006774.pdf [firstpage_image] =>[orig_patent_app_number] => 11768998 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4576550 [patent_doc_number] => 07822936 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-10-26 [patent_title] => 'Memory chip for high capacity memory subsystem supporting replication of command data' [patent_app_type] => utility [patent_app_number] => 11/769001 [patent_app_country] => US [patent_app_date] => 2007-06-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 14790 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 338 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/822/07822936.pdf [firstpage_image] =>[orig_patent_app_number] => 11769001 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4512456 [patent_doc_number] => 07921271 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-04-05 [patent_title] => 'Hub for supporting high capacity memory subsystem' [patent_app_type] => utility [patent_app_number] => 11/769019 [patent_app_country] => US [patent_app_date] => 2007-06-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 14887 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 458 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/921/07921271.pdf [firstpage_image] =>[orig_patent_app_number] => 11769019 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5071435 [patent_doc_number] => 20070192537 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-08-16 [patent_title] => 'Request processing order in a cache' [patent_app_type] => utility [patent_app_number] => 11/788607 [patent_app_country] => US [patent_app_date] => 2007-04-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2201 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0192/20070192537.pdf [firstpage_image] =>[orig_patent_app_number] => 11788607 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4741813 [patent_doc_number] => 20080235466 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-09-25 [patent_title] => 'Methods for storing memory operations in a queue' [patent_app_type] => utility [patent_app_number] => 11/726648 [patent_app_country] => US [patent_app_date] => 2007-03-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5058 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0235/20080235466.pdf [firstpage_image] =>[orig_patent_app_number] => 11726648 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4741834 [patent_doc_number] => 20080235487 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-09-25 [patent_title] => 'Applying quality of service (QoS) to a translation lookaside buffer (TLB)' [patent_app_type] => utility [patent_app_number] => 11/726316 [patent_app_country] => US [patent_app_date] => 2007-03-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3645 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0235/20080235487.pdf [firstpage_image] =>[orig_patent_app_number] => 11726316 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4741804 [patent_doc_number] => 20080235457 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-09-25 [patent_title] => 'Dynamic quality of service (QoS) for a shared cache' [patent_app_type] => utility [patent_app_number] => 11/726238 [patent_app_country] => US [patent_app_date] => 2007-03-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4439 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0235/20080235457.pdf [firstpage_image] =>[orig_patent_app_number] => 11726238 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4741827 [patent_doc_number] => 20080235480 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-09-25 [patent_title] => 'Systems for storing memory operations in a queue' [patent_app_type] => utility [patent_app_number] => 11/726646 [patent_app_country] => US [patent_app_date] => 2007-03-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5084 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0235/20080235480.pdf [firstpage_image] =>[orig_patent_app_number] => 11726646 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 28195 [patent_doc_number] => 07797500 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2010-09-14 [patent_title] => 'Geometry adaptation using data redistribution' [patent_app_type] => utility [patent_app_number] => 11/726311 [patent_app_country] => US [patent_app_date] => 2007-03-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 10368 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/797/07797500.pdf [firstpage_image] =>[orig_patent_app_number] => 11726311 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5071460 [patent_doc_number] => 20070192562 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-08-16 [patent_title] => 'Storage management method and storage management system' [patent_app_type] => utility [patent_app_number] => 11/723453 [patent_app_country] => US [patent_app_date] => 2007-03-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 8684 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0192/20070192562.pdf [firstpage_image] =>[orig_patent_app_number] => 11723453 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5121838 [patent_doc_number] => 20070143553 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-06-21 [patent_title] => 'Dynamic command and/or address mirroring system and method for memory modules' [patent_app_type] => utility [patent_app_number] => 11/706032 [patent_app_country] => US [patent_app_date] => 2007-02-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6790 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0143/20070143553.pdf [firstpage_image] =>[orig_patent_app_number] => 11706032 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5071431 [patent_doc_number] => 20070192533 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-08-16 [patent_title] => 'Apparatus and method for managing mapping information of nonvolatile memory' [patent_app_type] => utility [patent_app_number] => 11/655215 [patent_app_country] => US [patent_app_date] => 2007-01-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 4890 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0192/20070192533.pdf [firstpage_image] =>[orig_patent_app_number] => 11655215 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5102810 [patent_doc_number] => 20070186072 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-08-09 [patent_title] => 'Memory systems capable of reducing electromagnetic interference in data lines' [patent_app_type] => utility [patent_app_number] => 11/655194 [patent_app_country] => US [patent_app_date] => 2007-01-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4010 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0186/20070186072.pdf [firstpage_image] =>[orig_patent_app_number] => 11655194 [rel_patent_id] =>[rel_patent_doc_number] =>)