Search

Duc T. Doan

Examiner (ID: 14386, Phone: (571)272-4171 , Office: P/2135 )

Most Active Art Unit
2185
Art Unit(s)
2135, 2188, 2185
Total Applications
730
Issued Applications
596
Pending Applications
8
Abandoned Applications
129

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 908407 [patent_doc_number] => 07337281 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-02-26 [patent_title] => 'Storage system and data caching method in the system' [patent_app_type] => utility [patent_app_number] => 10/770007 [patent_app_country] => US [patent_app_date] => 2004-02-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 10439 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 474 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/337/07337281.pdf [firstpage_image] =>[orig_patent_app_number] => 10770007 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/770007
Storage system and data caching method in the system Feb 2, 2004 Issued
Array ( [id] => 7006751 [patent_doc_number] => 20050172064 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-08-04 [patent_title] => 'Method and apparatus for addressing in mass storage non-volatile memory devices' [patent_app_type] => utility [patent_app_number] => 10/766320 [patent_app_country] => US [patent_app_date] => 2004-01-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2567 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0172/20050172064.pdf [firstpage_image] =>[orig_patent_app_number] => 10766320 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/766320
Method and apparatus for addressing in mass storage non-volatile memory devices Jan 28, 2004 Abandoned
Array ( [id] => 7457040 [patent_doc_number] => 20040186966 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-09-23 [patent_title] => 'System chip and related method of data access' [patent_app_type] => new [patent_app_number] => 10/765897 [patent_app_country] => US [patent_app_date] => 2004-01-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2883 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 65 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0186/20040186966.pdf [firstpage_image] =>[orig_patent_app_number] => 10765897 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/765897
System chip and related method of data access Jan 28, 2004 Abandoned
Array ( [id] => 481255 [patent_doc_number] => 07228384 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-06-05 [patent_title] => 'Cache storage system that enables exclusion of locking of an area to be accessed' [patent_app_type] => utility [patent_app_number] => 10/764600 [patent_app_country] => US [patent_app_date] => 2004-01-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 9986 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 498 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/228/07228384.pdf [firstpage_image] =>[orig_patent_app_number] => 10764600 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/764600
Cache storage system that enables exclusion of locking of an area to be accessed Jan 26, 2004 Issued
Array ( [id] => 7207978 [patent_doc_number] => 20050166206 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-07-28 [patent_title] => 'Resource management in a processor-based system using hardware queues' [patent_app_type] => utility [patent_app_number] => 10/764967 [patent_app_country] => US [patent_app_date] => 2004-01-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6978 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0166/20050166206.pdf [firstpage_image] =>[orig_patent_app_number] => 10764967 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/764967
Resource management in a processor-based system using hardware queues Jan 25, 2004 Abandoned
Array ( [id] => 7206669 [patent_doc_number] => 20050166013 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-07-28 [patent_title] => 'System and method for selecting command for execution in HDD based on benefit' [patent_app_type] => utility [patent_app_number] => 10/764946 [patent_app_country] => US [patent_app_date] => 2004-01-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2227 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0166/20050166013.pdf [firstpage_image] =>[orig_patent_app_number] => 10764946 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/764946
System and method for selecting command for execution in HDD based on benefit Jan 25, 2004 Issued
Array ( [id] => 7206725 [patent_doc_number] => 20050166024 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-07-28 [patent_title] => 'Method and apparatus for operating multiple security modules' [patent_app_type] => utility [patent_app_number] => 10/764918 [patent_app_country] => US [patent_app_date] => 2004-01-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6742 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0166/20050166024.pdf [firstpage_image] =>[orig_patent_app_number] => 10764918 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/764918
Method and apparatus for operating multiple security modules Jan 25, 2004 Issued
Array ( [id] => 198171 [patent_doc_number] => 07639180 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-12-29 [patent_title] => 'Dynamic memory allocation and sharing in electronic systems' [patent_app_type] => utility [patent_app_number] => 10/762852 [patent_app_country] => US [patent_app_date] => 2004-01-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 12383 [patent_no_of_claims] => 52 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/639/07639180.pdf [firstpage_image] =>[orig_patent_app_number] => 10762852 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/762852
Dynamic memory allocation and sharing in electronic systems Jan 21, 2004 Issued
Array ( [id] => 609459 [patent_doc_number] => 07155563 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2006-12-26 [patent_title] => 'Circuits to generate a sequential index for an input number in a pre-defined list of numbers' [patent_app_type] => utility [patent_app_number] => 10/763020 [patent_app_country] => US [patent_app_date] => 2004-01-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 1558 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 219 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/155/07155563.pdf [firstpage_image] =>[orig_patent_app_number] => 10763020 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/763020
Circuits to generate a sequential index for an input number in a pre-defined list of numbers Jan 20, 2004 Issued
Array ( [id] => 7442862 [patent_doc_number] => 20040210724 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-10-21 [patent_title] => 'Block data migration' [patent_app_type] => new [patent_app_number] => 10/762984 [patent_app_country] => US [patent_app_date] => 2004-01-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 7864 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0210/20040210724.pdf [firstpage_image] =>[orig_patent_app_number] => 10762984 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/762984
Block data migration Jan 20, 2004 Abandoned
Array ( [id] => 581617 [patent_doc_number] => 07159078 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-01-02 [patent_title] => 'Computer system embedding sequential buffers therein for performing a digital signal processing data access operation and a method thereof' [patent_app_type] => utility [patent_app_number] => 10/762170 [patent_app_country] => US [patent_app_date] => 2004-01-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2291 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/159/07159078.pdf [firstpage_image] =>[orig_patent_app_number] => 10762170 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/762170
Computer system embedding sequential buffers therein for performing a digital signal processing data access operation and a method thereof Jan 20, 2004 Issued
Array ( [id] => 7042162 [patent_doc_number] => 20050160218 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-07-21 [patent_title] => 'Highly integrated mass storage device with an intelligent flash controller' [patent_app_type] => utility [patent_app_number] => 10/761853 [patent_app_country] => US [patent_app_date] => 2004-01-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3733 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0160/20050160218.pdf [firstpage_image] =>[orig_patent_app_number] => 10761853 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/761853
Highly integrated mass storage device with an intelligent flash controller Jan 19, 2004 Abandoned
Array ( [id] => 4472177 [patent_doc_number] => 07937551 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-05-03 [patent_title] => 'Storage systems having differentiated storage pools' [patent_app_type] => utility [patent_app_number] => 10/761884 [patent_app_country] => US [patent_app_date] => 2004-01-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3641 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 179 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/937/07937551.pdf [firstpage_image] =>[orig_patent_app_number] => 10761884 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/761884
Storage systems having differentiated storage pools Jan 19, 2004 Issued
Array ( [id] => 6999614 [patent_doc_number] => 20050138306 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-06-23 [patent_title] => 'Performance of operations on selected data in a storage area' [patent_app_type] => utility [patent_app_number] => 10/742128 [patent_app_country] => US [patent_app_date] => 2003-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 9129 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0138/20050138306.pdf [firstpage_image] =>[orig_patent_app_number] => 10742128 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/742128
Performance of operations on selected data in a storage area Dec 18, 2003 Abandoned
Array ( [id] => 7328668 [patent_doc_number] => 20040139285 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-07-15 [patent_title] => 'Memory component with multiple transfer formats' [patent_app_type] => new [patent_app_number] => 10/739669 [patent_app_country] => US [patent_app_date] => 2003-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 23 [patent_no_of_words] => 30938 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 21 [patent_words_short_claim] => 30 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0139/20040139285.pdf [firstpage_image] =>[orig_patent_app_number] => 10739669 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/739669
Memory component with multiple transfer formats Dec 17, 2003 Abandoned
Array ( [id] => 6999600 [patent_doc_number] => 20050138298 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-06-23 [patent_title] => 'Secondary path for coherency controller to interconnection network(s)' [patent_app_type] => utility [patent_app_number] => 10/739694 [patent_app_country] => US [patent_app_date] => 2003-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4346 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0138/20050138298.pdf [firstpage_image] =>[orig_patent_app_number] => 10739694 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/739694
Secondary path for coherency controller to interconnection network(s) Dec 17, 2003 Issued
Array ( [id] => 6999547 [patent_doc_number] => 20050138281 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-06-23 [patent_title] => 'Request processing order in a cache' [patent_app_type] => utility [patent_app_number] => 10/739921 [patent_app_country] => US [patent_app_date] => 2003-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2178 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0138/20050138281.pdf [firstpage_image] =>[orig_patent_app_number] => 10739921 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/739921
Request processing order in a cache Dec 17, 2003 Abandoned
Array ( [id] => 534389 [patent_doc_number] => 07194585 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-03-20 [patent_title] => 'Coherency controller management of transactions' [patent_app_type] => utility [patent_app_number] => 10/739698 [patent_app_country] => US [patent_app_date] => 2003-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 6044 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/194/07194585.pdf [firstpage_image] =>[orig_patent_app_number] => 10739698 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/739698
Coherency controller management of transactions Dec 17, 2003 Issued
Array ( [id] => 7341261 [patent_doc_number] => 20040133736 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-07-08 [patent_title] => 'Memory module device for use in high-frequency operation' [patent_app_type] => new [patent_app_number] => 10/739991 [patent_app_country] => US [patent_app_date] => 2003-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2519 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0133/20040133736.pdf [firstpage_image] =>[orig_patent_app_number] => 10739991 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/739991
Memory module device for use in high-frequency operation Dec 17, 2003 Issued
Array ( [id] => 7341225 [patent_doc_number] => 20040133729 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-07-08 [patent_title] => 'Memory component with synchronous data transfer' [patent_app_type] => new [patent_app_number] => 10/740012 [patent_app_country] => US [patent_app_date] => 2003-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 23 [patent_no_of_words] => 30954 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 21 [patent_words_short_claim] => 30 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0133/20040133729.pdf [firstpage_image] =>[orig_patent_app_number] => 10740012 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/740012
Memory component with synchronous data transfer Dec 17, 2003 Abandoned
Menu