Array
(
[id] => 6636923
[patent_doc_number] => 20020016878
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2002-02-07
[patent_title] => 'Technique for guaranteeing the availability of per thread storage in a distributed computing environment'
[patent_app_type] => new
[patent_app_number] => 09/912833
[patent_app_country] => US
[patent_app_date] => 2001-07-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 5494
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 47
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0016/20020016878.pdf
[firstpage_image] =>[orig_patent_app_number] => 09912833
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/912833 | Technique for guaranteeing the availability of per thread storage in a distributed computing environment | Jul 24, 2001 | Abandoned |
Array
(
[id] => 6844495
[patent_doc_number] => 20030149842
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2003-08-07
[patent_title] => 'Method for controling cache system comprising direct-mapped cache and fully-associative buffer'
[patent_app_type] => new
[patent_app_number] => 10/258074
[patent_app_country] => US
[patent_app_date] => 2003-01-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 3769
[patent_no_of_claims] => 4
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 126
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0149/20030149842.pdf
[firstpage_image] =>[orig_patent_app_number] => 10258074
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/258074 | Cache system and method for controlling the cache system comprising direct-mapped cache and fully-associative buffer | May 15, 2001 | Issued |
Array
(
[id] => 777881
[patent_doc_number] => 07003643
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2006-02-21
[patent_title] => 'Burst counter controller and method in a memory device operable in a 2-bit prefetch mode'
[patent_app_type] => utility
[patent_app_number] => 09/836593
[patent_app_country] => US
[patent_app_date] => 2001-04-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 4
[patent_no_of_words] => 4111
[patent_no_of_claims] => 24
[patent_no_of_ind_claims] => 9
[patent_words_short_claim] => 64
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/003/07003643.pdf
[firstpage_image] =>[orig_patent_app_number] => 09836593
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/836593 | Burst counter controller and method in a memory device operable in a 2-bit prefetch mode | Apr 15, 2001 | Issued |
Array
(
[id] => 5790775
[patent_doc_number] => 20020161698
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2002-10-31
[patent_title] => 'Caching system using timing queues based on last access times'
[patent_app_type] => new
[patent_app_number] => 09/790680
[patent_app_country] => US
[patent_app_date] => 2001-02-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 3363
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 63
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0161/20020161698.pdf
[firstpage_image] =>[orig_patent_app_number] => 09790680
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/790680 | Caching system using timing queues based on last access times | Feb 22, 2001 | Abandoned |
