Search

Dung T Nguyen

Examiner (ID: 10437, Phone: (571)272-2297 , Office: P/2871 )

Most Active Art Unit
2871
Art Unit(s)
2871, 2828
Total Applications
3235
Issued Applications
2619
Pending Applications
178
Abandoned Applications
437

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 15625791 [patent_doc_number] => 20200083300 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-03-12 [patent_title] => Display Device and Method for Manufacturing Display Device [patent_app_type] => utility [patent_app_number] => 16/686556 [patent_app_country] => US [patent_app_date] => 2019-11-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 20859 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16686556 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/686556
Display device comprising a light-emitting element Nov 17, 2019 Issued
Array ( [id] => 16226533 [patent_doc_number] => 20200251650 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-08-06 [patent_title] => MAGNETIC TUNNEL JUNCTION AND MAGNETIC MEMORY DEVICE COMPRISING THE SAME [patent_app_type] => utility [patent_app_number] => 16/685415 [patent_app_country] => US [patent_app_date] => 2019-11-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7361 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16685415 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/685415
Magnetic tunnel junction including a free layer structure and magnetic memory device comprising the same Nov 14, 2019 Issued
Array ( [id] => 16828030 [patent_doc_number] => 20210143323 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-05-13 [patent_title] => Methods for etching a structure for MRAM Applications [patent_app_type] => utility [patent_app_number] => 16/681351 [patent_app_country] => US [patent_app_date] => 2019-11-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9453 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16681351 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/681351
Methods for etching a structure for MRAM applications Nov 11, 2019 Issued
Array ( [id] => 15597917 [patent_doc_number] => 20200075493 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-03-05 [patent_title] => MULTI-CHIP PACKAGE AND METHOD OF PROVIDING DIE-TO-DIE INTERCONNECTS IN SAME [patent_app_type] => utility [patent_app_number] => 16/677533 [patent_app_country] => US [patent_app_date] => 2019-11-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10181 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 52 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16677533 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/677533
Multi-chip package and method of providing die-to-die interconnects in same Nov 6, 2019 Issued
Array ( [id] => 17210903 [patent_doc_number] => 11171283 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-11-09 [patent_title] => Modified double magnetic tunnel junction structure suitable for BEOL integration [patent_app_type] => utility [patent_app_number] => 16/671995 [patent_app_country] => US [patent_app_date] => 2019-11-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 6877 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16671995 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/671995
Modified double magnetic tunnel junction structure suitable for BEOL integration Oct 31, 2019 Issued
Array ( [id] => 15564089 [patent_doc_number] => 20200066456 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-02-27 [patent_title] => Apparatuses, Multi-Chip Modules and Capacitive Chips [patent_app_type] => utility [patent_app_number] => 16/666128 [patent_app_country] => US [patent_app_date] => 2019-10-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6609 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16666128 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/666128
Apparatuses, multi-chip modules and capacitive chips Oct 27, 2019 Issued
Array ( [id] => 17278217 [patent_doc_number] => 20210384415 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-12-09 [patent_title] => MAGNETORESISTIVE DEVICES AND METHODS THEREFOR [patent_app_type] => utility [patent_app_number] => 17/285364 [patent_app_country] => US [patent_app_date] => 2019-10-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11743 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17285364 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/285364
Magnetoresistive devices and methods therefor Oct 16, 2019 Issued
Array ( [id] => 15641363 [patent_doc_number] => 10593686 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-03-17 [patent_title] => Non-volatile memory device [patent_app_type] => utility [patent_app_number] => 16/591433 [patent_app_country] => US [patent_app_date] => 2019-10-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 37 [patent_no_of_words] => 5848 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 212 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16591433 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/591433
Non-volatile memory device Oct 1, 2019 Issued
Array ( [id] => 15442851 [patent_doc_number] => 20200035609 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-01-30 [patent_title] => ELECTRICAL JUNCTION [patent_app_type] => utility [patent_app_number] => 16/587959 [patent_app_country] => US [patent_app_date] => 2019-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4405 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16587959 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/587959
Electrical junction Sep 29, 2019 Issued
Array ( [id] => 15351863 [patent_doc_number] => 20200013823 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-01-09 [patent_title] => SEMICONDUCTOR PACKAGING METHOD AND SEMICONDUCTOR DEVICE BASED ON MOLDING PROCESS [patent_app_type] => utility [patent_app_number] => 16/578014 [patent_app_country] => US [patent_app_date] => 2019-09-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13322 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -20 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16578014 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/578014
Semiconductor packaging method and semiconductor device based on molding process Sep 19, 2019 Issued
Array ( [id] => 15351783 [patent_doc_number] => 20200013783 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-01-09 [patent_title] => METHOD FOR FORMING DYNAMIC RANDOM ACCESS MEMORY STRUCTURE [patent_app_type] => utility [patent_app_number] => 16/571202 [patent_app_country] => US [patent_app_date] => 2019-09-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3843 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -10 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16571202 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/571202
Method for forming dynamic random access memory structure Sep 15, 2019 Issued
Array ( [id] => 15299977 [patent_doc_number] => 20190393124 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-12-26 [patent_title] => ARRANGEMENT AND THERMAL MANAGEMENT OF 3D STACKED DIES [patent_app_type] => utility [patent_app_number] => 16/563138 [patent_app_country] => US [patent_app_date] => 2019-09-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4594 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16563138 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/563138
Arrangement and thermal management of 3D stacked dies Sep 5, 2019 Issued
Array ( [id] => 15299975 [patent_doc_number] => 20190393123 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-12-26 [patent_title] => ARRANGEMENT AND THERMAL MANAGEMENT OF 3D STACKED DIES [patent_app_type] => utility [patent_app_number] => 16/563077 [patent_app_country] => US [patent_app_date] => 2019-09-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4594 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 60 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16563077 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/563077
Arrangement and thermal management of 3D stacked dies Sep 5, 2019 Issued
Array ( [id] => 15260291 [patent_doc_number] => 20190378879 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-12-12 [patent_title] => Non-Linear Resistive Change Memory Cells and Arrays [patent_app_type] => utility [patent_app_number] => 16/544025 [patent_app_country] => US [patent_app_date] => 2019-08-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 63628 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 260 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16544025 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/544025
Non-linear resistive change memory cells and arrays Aug 18, 2019 Issued
Array ( [id] => 16187237 [patent_doc_number] => 10720579 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-07-21 [patent_title] => Self-selecting memory cell with dielectric barrier [patent_app_type] => utility [patent_app_number] => 16/537119 [patent_app_country] => US [patent_app_date] => 2019-08-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 18 [patent_no_of_words] => 12582 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16537119 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/537119
Self-selecting memory cell with dielectric barrier Aug 8, 2019 Issued
Array ( [id] => 15791667 [patent_doc_number] => 10629565 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-04-21 [patent_title] => Semiconductor device and method of forming SIP with electrical component terminals extending out from encapsulant [patent_app_type] => utility [patent_app_number] => 16/531593 [patent_app_country] => US [patent_app_date] => 2019-08-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 16 [patent_no_of_words] => 3221 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 32 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16531593 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/531593
Semiconductor device and method of forming SIP with electrical component terminals extending out from encapsulant Aug 4, 2019 Issued
Array ( [id] => 15093073 [patent_doc_number] => 20190341348 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-11-07 [patent_title] => ELECTRICAL FUSE AND/OR RESISTOR STRUCTURES [patent_app_type] => utility [patent_app_number] => 16/514333 [patent_app_country] => US [patent_app_date] => 2019-07-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3777 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16514333 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/514333
Electrical fuse and/or resistor structures Jul 16, 2019 Issued
Array ( [id] => 17310371 [patent_doc_number] => 11211498 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-12-28 [patent_title] => FinFETs with wrap-around silicide and method forming the same [patent_app_type] => utility [patent_app_number] => 16/511493 [patent_app_country] => US [patent_app_date] => 2019-07-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 37 [patent_figures_cnt] => 63 [patent_no_of_words] => 8996 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 65 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16511493 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/511493
FinFETs with wrap-around silicide and method forming the same Jul 14, 2019 Issued
Array ( [id] => 15939241 [patent_doc_number] => 20200161254 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-05-21 [patent_title] => METHODS AND MODULES RELATED TO SHIELDED LEAD FRAME PACKAGES [patent_app_type] => utility [patent_app_number] => 16/458011 [patent_app_country] => US [patent_app_date] => 2019-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6077 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => 0 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16458011 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/458011
Methods and modules related to shielded lead frame packages Jun 28, 2019 Issued
Array ( [id] => 15000307 [patent_doc_number] => 20190319111 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-10-17 [patent_title] => GROUP IIIA-N HEMT WITH A TUNNEL DIODE IN THE GATE STACK [patent_app_type] => utility [patent_app_number] => 16/456040 [patent_app_country] => US [patent_app_date] => 2019-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5166 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 36 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16456040 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/456040
Group IIIA-N HEMT with a tunnel diode in the gate stack Jun 27, 2019 Issued
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