Search

Dung T Nguyen

Examiner (ID: 10437, Phone: (571)272-2297 , Office: P/2871 )

Most Active Art Unit
2871
Art Unit(s)
2871, 2828
Total Applications
3235
Issued Applications
2619
Pending Applications
178
Abandoned Applications
437

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 12154808 [patent_doc_number] => 20180026070 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-01-25 [patent_title] => 'Semiconductor Device and Electronic Device' [patent_app_type] => utility [patent_app_number] => 15/708527 [patent_app_country] => US [patent_app_date] => 2017-09-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 44 [patent_figures_cnt] => 44 [patent_no_of_words] => 37254 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15708527 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/708527
Semiconductor device and electronic device Sep 18, 2017 Issued
Array ( [id] => 14204565 [patent_doc_number] => 10269400 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-04-23 [patent_title] => Tilted synthetic antiferromagnet polarizer/reference layer for STT-MRAM bits [patent_app_type] => utility [patent_app_number] => 15/696637 [patent_app_country] => US [patent_app_date] => 2017-09-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 4521 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15696637 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/696637
Tilted synthetic antiferromagnet polarizer/reference layer for STT-MRAM bits Sep 5, 2017 Issued
Array ( [id] => 14093625 [patent_doc_number] => 10242725 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-03-26 [patent_title] => Modular magnetoresistive memory [patent_app_type] => utility [patent_app_number] => 15/694139 [patent_app_country] => US [patent_app_date] => 2017-09-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 17 [patent_no_of_words] => 5019 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15694139 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/694139
Modular magnetoresistive memory Aug 31, 2017 Issued
Array ( [id] => 17332453 [patent_doc_number] => 11222921 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-01-11 [patent_title] => Selector devices [patent_app_type] => utility [patent_app_number] => 16/635111 [patent_app_country] => US [patent_app_date] => 2017-08-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 9 [patent_no_of_words] => 7985 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 46 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16635111 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/635111
Selector devices Aug 28, 2017 Issued
Array ( [id] => 13349591 [patent_doc_number] => 20180226335 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-08-09 [patent_title] => SEMICONDUCTOR INTEGRATED CIRCUIT [patent_app_type] => utility [patent_app_number] => 15/686904 [patent_app_country] => US [patent_app_date] => 2017-08-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9485 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 193 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15686904 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/686904
Semiconductor integrated circuit including discharge control circuit Aug 24, 2017 Issued
Array ( [id] => 14920381 [patent_doc_number] => 10431517 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-10-01 [patent_title] => Arrangement and thermal management of 3D stacked dies [patent_app_type] => utility [patent_app_number] => 15/686558 [patent_app_country] => US [patent_app_date] => 2017-08-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 13 [patent_no_of_words] => 4581 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 62 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15686558 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/686558
Arrangement and thermal management of 3D stacked dies Aug 24, 2017 Issued
Array ( [id] => 13996103 [patent_doc_number] => 20190067209 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-02-28 [patent_title] => Compressive Interlayer Having a Defined Crack-Stop Edge Extension [patent_app_type] => utility [patent_app_number] => 15/686576 [patent_app_country] => US [patent_app_date] => 2017-08-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4150 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -26 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15686576 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/686576
Compressive interlayer having a defined crack-stop edge extension Aug 24, 2017 Issued
Array ( [id] => 15169911 [patent_doc_number] => 10490459 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-11-26 [patent_title] => Method for source/drain contact formation in semiconductor devices [patent_app_type] => utility [patent_app_number] => 15/686698 [patent_app_country] => US [patent_app_date] => 2017-08-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 22 [patent_no_of_words] => 7624 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15686698 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/686698
Method for source/drain contact formation in semiconductor devices Aug 24, 2017 Issued
Array ( [id] => 14205699 [patent_doc_number] => 10269977 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-04-23 [patent_title] => Semiconductor device including oxide semiconductor layer having regions with different resistances [patent_app_type] => utility [patent_app_number] => 15/686831 [patent_app_country] => US [patent_app_date] => 2017-08-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 9357 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15686831 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/686831
Semiconductor device including oxide semiconductor layer having regions with different resistances Aug 24, 2017 Issued
Array ( [id] => 14859213 [patent_doc_number] => 10418341 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-09-17 [patent_title] => Semiconductor device and method of forming SIP with electrical component terminals extending out from encapsulant [patent_app_type] => utility [patent_app_number] => 15/686584 [patent_app_country] => US [patent_app_date] => 2017-08-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 16 [patent_no_of_words] => 3201 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 41 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15686584 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/686584
Semiconductor device and method of forming SIP with electrical component terminals extending out from encapsulant Aug 24, 2017 Issued
Array ( [id] => 14889353 [patent_doc_number] => 10424728 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-09-24 [patent_title] => Self-selecting memory cell with dielectric barrier [patent_app_type] => utility [patent_app_number] => 15/687038 [patent_app_country] => US [patent_app_date] => 2017-08-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 18 [patent_no_of_words] => 12535 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 56 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15687038 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/687038
Self-selecting memory cell with dielectric barrier Aug 24, 2017 Issued
Array ( [id] => 13630079 [patent_doc_number] => 20180366592 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-12-20 [patent_title] => SELF-ALIGNED CONTACT (SAC) ON GATE FOR IMPROVING METAL OXIDE SEMICONDUCTOR (MOS) VARACTOR QUALITY FACTOR [patent_app_type] => utility [patent_app_number] => 15/686827 [patent_app_country] => US [patent_app_date] => 2017-08-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7785 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15686827 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/686827
Self-aligned contact (SAC) on gate for improving metal oxide semiconductor (MOS) varactor quality factor Aug 24, 2017 Issued
Array ( [id] => 13993647 [patent_doc_number] => 20190065981 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-02-28 [patent_title] => MAGNETIC FLUX CONTROL IN SUPERCONDUCTING DEVICE [patent_app_type] => utility [patent_app_number] => 15/686902 [patent_app_country] => US [patent_app_date] => 2017-08-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9864 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -25 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15686902 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/686902
Magnetic flux control in superconducting device Aug 24, 2017 Issued
Array ( [id] => 12243243 [patent_doc_number] => 20180076106 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-03-15 [patent_title] => 'SEMICONDUCTOR DEVICE AND METHOD OF MAKING THE SAME' [patent_app_type] => utility [patent_app_number] => 15/686930 [patent_app_country] => US [patent_app_date] => 2017-08-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 24 [patent_no_of_words] => 12425 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15686930 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/686930
Semiconductor package and method of making the same Aug 24, 2017 Issued
Array ( [id] => 14459625 [patent_doc_number] => 10325784 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-06-18 [patent_title] => Method for manufacturing an encapsulation cover for an electronic package and electronic package comprising a cover [patent_app_type] => utility [patent_app_number] => 15/685552 [patent_app_country] => US [patent_app_date] => 2017-08-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 19 [patent_no_of_words] => 5554 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15685552 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/685552
Method for manufacturing an encapsulation cover for an electronic package and electronic package comprising a cover Aug 23, 2017 Issued
Array ( [id] => 13257583 [patent_doc_number] => 10141489 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2018-11-27 [patent_title] => LED illumination apparatus [patent_app_type] => utility [patent_app_number] => 15/685621 [patent_app_country] => US [patent_app_date] => 2017-08-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 17 [patent_no_of_words] => 4619 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 199 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15685621 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/685621
LED illumination apparatus Aug 23, 2017 Issued
Array ( [id] => 13132219 [patent_doc_number] => 10084049 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-09-25 [patent_title] => Semiconductor device [patent_app_type] => utility [patent_app_number] => 15/685255 [patent_app_country] => US [patent_app_date] => 2017-08-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 27 [patent_figures_cnt] => 40 [patent_no_of_words] => 10186 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15685255 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/685255
Semiconductor device Aug 23, 2017 Issued
Array ( [id] => 14063921 [patent_doc_number] => 10236263 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2019-03-19 [patent_title] => Methods and structures for mitigating ESD during wafer bonding [patent_app_type] => utility [patent_app_number] => 15/685564 [patent_app_country] => US [patent_app_date] => 2017-08-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 13 [patent_no_of_words] => 4980 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 168 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15685564 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/685564
Methods and structures for mitigating ESD during wafer bonding Aug 23, 2017 Issued
Array ( [id] => 12990286 [patent_doc_number] => 20170345838 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-11-30 [patent_title] => NON-VOLATILE MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 15/678853 [patent_app_country] => US [patent_app_date] => 2017-08-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5810 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 192 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15678853 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/678853
Non-volatile memory device Aug 15, 2017 Issued
Array ( [id] => 12989554 [patent_doc_number] => 20170345578 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-11-30 [patent_title] => Apparatuses, Multi-Chip Modules and Capacitive Chips [patent_app_type] => utility [patent_app_number] => 15/675977 [patent_app_country] => US [patent_app_date] => 2017-08-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6456 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -23 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15675977 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/675977
Apparatuses, multi-chip modules and capacitive chips Aug 13, 2017 Issued
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