![](/images/general/no_picture/200_user.png)
Duy K Le
Examiner (ID: 11414)
Most Active Art Unit | 2685 |
Art Unit(s) | 2685 |
Total Applications | 38 |
Issued Applications | 13 |
Pending Applications | 3 |
Abandoned Applications | 22 |
Applications
Application number | Title of the application | Filing Date | Status |
---|---|---|---|
Array
(
[id] => 14364605
[patent_doc_number] => 10303608
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2019-05-28
[patent_title] => Intelligent data prefetching using address delta prediction
[patent_app_type] => utility
[patent_app_number] => 15/683391
[patent_app_country] => US
[patent_app_date] => 2017-08-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 12
[patent_no_of_words] => 6469
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 234
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15683391
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/683391 | Intelligent data prefetching using address delta prediction | Aug 21, 2017 | Issued |
Array
(
[id] => 13992453
[patent_doc_number] => 20190065384
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2019-02-28
[patent_title] => EXPEDITING CACHE MISSES THROUGH CACHE HIT PREDICTION
[patent_app_type] => utility
[patent_app_number] => 15/683350
[patent_app_country] => US
[patent_app_date] => 2017-08-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 6327
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -24
[patent_words_short_claim] => 84
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15683350
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/683350 | EXPEDITING CACHE MISSES THROUGH CACHE HIT PREDICTION | Aug 21, 2017 | Abandoned |
15/683700 | Multi-Level Caching In A Storage System With A Configurable Non-Volatile Memory Interface Controller Topology | Aug 21, 2017 | Abandoned |
Array
(
[id] => 13992481
[patent_doc_number] => 20190065398
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2019-02-28
[patent_title] => ENSURING FORWARD PROGRESS FOR NESTED TRANSLATIONS IN A MEMORY MANAGEMENT UNIT
[patent_app_type] => utility
[patent_app_number] => 15/683615
[patent_app_country] => US
[patent_app_date] => 2017-08-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 6065
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -11
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15683615
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/683615 | Ensuring forward progress for nested translations in a memory management unit | Aug 21, 2017 | Issued |
Array
(
[id] => 13579761
[patent_doc_number] => 20180341429
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2018-11-29
[patent_title] => Non-Volatile Memory Over Fabric Controller with Memory Bypass
[patent_app_type] => utility
[patent_app_number] => 15/683710
[patent_app_country] => US
[patent_app_date] => 2017-08-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 11947
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15683710
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/683710 | Non-volatile memory over fabric controller with memory bypass | Aug 21, 2017 | Issued |
Array
(
[id] => 12989224
[patent_doc_number] => 20170345467
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2017-11-30
[patent_title] => INDIRECT REGISTER ACCESS METHOD AND SYSTEM
[patent_app_type] => utility
[patent_app_number] => 15/676796
[patent_app_country] => US
[patent_app_date] => 2017-08-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 10283
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -22
[patent_words_short_claim] => 105
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15676796
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/676796 | Indirect register access method and system | Aug 13, 2017 | Issued |
Array
(
[id] => 18622184
[patent_doc_number] => 11755224
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2023-09-12
[patent_title] => Storing data in slices of different sizes within different storage tiers
[patent_app_type] => utility
[patent_app_number] => 16/078378
[patent_app_country] => US
[patent_app_date] => 2017-07-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 16
[patent_figures_cnt] => 16
[patent_no_of_words] => 19949
[patent_no_of_claims] => 27
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 357
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16078378
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/078378 | Storing data in slices of different sizes within different storage tiers | Jul 26, 2017 | Issued |
Array
(
[id] => 14555677
[patent_doc_number] => 10346300
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2019-07-09
[patent_title] => Providing multiple memory modes for a processor including internal memory
[patent_app_type] => utility
[patent_app_number] => 15/628811
[patent_app_country] => US
[patent_app_date] => 2017-06-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 16
[patent_figures_cnt] => 17
[patent_no_of_words] => 13084
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 161
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15628811
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/628811 | Providing multiple memory modes for a processor including internal memory | Jun 20, 2017 | Issued |
Array
(
[id] => 12161006
[patent_doc_number] => 20180032272
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2018-02-01
[patent_title] => 'INFORMATION PROCESSING DEVICE AND MEMORY CONTROLLER'
[patent_app_type] => utility
[patent_app_number] => 15/616989
[patent_app_country] => US
[patent_app_date] => 2017-06-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 24
[patent_figures_cnt] => 24
[patent_no_of_words] => 9874
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15616989
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/616989 | Information processing device and memory controller | Jun 7, 2017 | Issued |
Array
(
[id] => 13482947
[patent_doc_number] => 20180293016
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2018-10-11
[patent_title] => METHOD AND APPARATUS FOR UPDATING DATA IN A MEMORY FOR ELECTRICAL COMPENSATION
[patent_app_type] => utility
[patent_app_number] => 15/567733
[patent_app_country] => US
[patent_app_date] => 2017-05-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 3610
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -14
[patent_words_short_claim] => 41
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15567733
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/567733 | Method and apparatus for updating data in a memory for electrical compensation | May 16, 2017 | Issued |
Array
(
[id] => 11945101
[patent_doc_number] => 20170249253
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2017-08-31
[patent_title] => 'MICROPROCESSOR ARCHITECTURE HAVING ALTERNATIVE MEMORY ACCESS PATHS'
[patent_app_type] => utility
[patent_app_number] => 15/596649
[patent_app_country] => US
[patent_app_date] => 2017-05-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 8715
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15596649
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/596649 | Microprocessor architecture having alternative memory access paths | May 15, 2017 | Issued |
Array
(
[id] => 14750831
[patent_doc_number] => 20190258589
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2019-08-22
[patent_title] => STORAGE DEVICE INCLUDING ONLY OWNER-WRITABLE BOOT AREA
[patent_app_type] => utility
[patent_app_number] => 16/344895
[patent_app_country] => US
[patent_app_date] => 2017-04-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 2171
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -3
[patent_words_short_claim] => 116
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16344895
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/344895 | STORAGE DEVICE INCLUDING ONLY OWNER-WRITABLE BOOT AREA | Apr 25, 2017 | Abandoned |
Array
(
[id] => 11965684
[patent_doc_number] => 20170269837
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2017-09-21
[patent_title] => 'USING COUNTERS AND A TABLE TO PROTECT DATA IN A STORAGE DEVICE'
[patent_app_type] => utility
[patent_app_number] => 15/479224
[patent_app_country] => US
[patent_app_date] => 2017-04-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 6676
[patent_no_of_claims] => 26
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15479224
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/479224 | USING COUNTERS AND A TABLE TO PROTECT DATA IN A STORAGE DEVICE | Apr 3, 2017 | Abandoned |
Array
(
[id] => 11745749
[patent_doc_number] => 20170199822
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2017-07-13
[patent_title] => 'SYSTEMS AND METHODS FOR ACQUIRING DATA FOR LOADS AT DIFFERENT ACCESS TIMES FROM HIERARCHICAL SOURCES USING A LOAD QUEUE AS A TEMPORARY STORAGE BUFFER AND COMPLETING THE LOAD EARLY'
[patent_app_type] => utility
[patent_app_number] => 15/469457
[patent_app_country] => US
[patent_app_date] => 2017-03-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 4383
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15469457
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/469457 | Systems and methods for acquiring data for loads at different access times from hierarchical sources using a load queue as a temporary storage buffer and completing the load early | Mar 23, 2017 | Issued |
Array
(
[id] => 11731451
[patent_doc_number] => 20170192894
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2017-07-06
[patent_title] => 'DATA CACHE VIRTUAL HINT WAY PREDICTION, AND APPLICATIONS THEREOF'
[patent_app_type] => utility
[patent_app_number] => 15/467661
[patent_app_country] => US
[patent_app_date] => 2017-03-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 21
[patent_figures_cnt] => 21
[patent_no_of_words] => 12071
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15467661
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/467661 | Data cache virtual hint way prediction, and applications thereof | Mar 22, 2017 | Issued |
Array
(
[id] => 12713341
[patent_doc_number] => 20180129613
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2018-05-10
[patent_title] => CACHE MEMORY ARCHITECTURE AND POLICIES FOR ACCELERATING GRAPH ALGORITHMS
[patent_app_type] => utility
[patent_app_number] => 15/440400
[patent_app_country] => US
[patent_app_date] => 2017-02-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 6978
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 153
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15440400
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/440400 | Cache memory architecture and policies for accelerating graph algorithms | Feb 22, 2017 | Issued |
Array
(
[id] => 14394903
[patent_doc_number] => 10310735
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2019-06-04
[patent_title] => Data storage
[patent_app_type] => utility
[patent_app_number] => 15/440254
[patent_app_country] => US
[patent_app_date] => 2017-02-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 8
[patent_no_of_words] => 6200
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 156
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15440254
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/440254 | Data storage | Feb 22, 2017 | Issued |
Array
(
[id] => 16322930
[patent_doc_number] => 10782893
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2020-09-22
[patent_title] => Inhibiting tracks within a volume of a storage system
[patent_app_type] => utility
[patent_app_number] => 15/439805
[patent_app_country] => US
[patent_app_date] => 2017-02-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 7462
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 326
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15439805
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/439805 | Inhibiting tracks within a volume of a storage system | Feb 21, 2017 | Issued |
Array
(
[id] => 15136691
[patent_doc_number] => 10481812
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2019-11-19
[patent_title] => Storage device and information processing system
[patent_app_type] => utility
[patent_app_number] => 15/439880
[patent_app_country] => US
[patent_app_date] => 2017-02-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 14
[patent_figures_cnt] => 15
[patent_no_of_words] => 17975
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 377
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15439880
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/439880 | Storage device and information processing system | Feb 21, 2017 | Issued |
Array
(
[id] => 12256038
[patent_doc_number] => 09928180
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2018-03-27
[patent_title] => 'Synchronizing a translation lookaside buffer with page tables'
[patent_app_type] => utility
[patent_app_number] => 15/437369
[patent_app_country] => US
[patent_app_date] => 2017-02-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 11
[patent_no_of_words] => 9056
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 240
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15437369
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/437369 | Synchronizing a translation lookaside buffer with page tables | Feb 19, 2017 | Issued |