
Duy T. V. Nguyen
Examiner (ID: 10805, Phone: (571)270-7431 , Office: P/2894 )
| Most Active Art Unit | 2894 |
| Art Unit(s) | 2818, 4136, 2894 |
| Total Applications | 1217 |
| Issued Applications | 888 |
| Pending Applications | 152 |
| Abandoned Applications | 240 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 19054877
[patent_doc_number] => 20240096846
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-03-21
[patent_title] => BONDING APPARATUS AND BONDING METHOD
[patent_app_type] => utility
[patent_app_number] => 18/467071
[patent_app_country] => US
[patent_app_date] => 2023-09-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 11872
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -6
[patent_words_short_claim] => 218
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18467071
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/467071 | BONDING APPARATUS AND BONDING METHOD | Sep 13, 2023 | Pending |
Array
(
[id] => 19054877
[patent_doc_number] => 20240096846
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-03-21
[patent_title] => BONDING APPARATUS AND BONDING METHOD
[patent_app_type] => utility
[patent_app_number] => 18/467071
[patent_app_country] => US
[patent_app_date] => 2023-09-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 11872
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -6
[patent_words_short_claim] => 218
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18467071
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/467071 | BONDING APPARATUS AND BONDING METHOD | Sep 13, 2023 | Pending |
Array
(
[id] => 18866053
[patent_doc_number] => 20230420490
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-12-28
[patent_title] => METHOD OF MANUFACTURING METAL NITRIDE FILM AND ELECTRONIC DEVICE INCLUDING METAL NITRIDE FILM
[patent_app_type] => utility
[patent_app_number] => 18/465439
[patent_app_country] => US
[patent_app_date] => 2023-09-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 8879
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -11
[patent_words_short_claim] => 93
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18465439
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/465439 | Method of manufacturing metal nitride film and electronic device including metal nitride film | Sep 11, 2023 | Issued |
Array
(
[id] => 18866165
[patent_doc_number] => 20230420602
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-12-28
[patent_title] => MICROELECTRONIC WORKPIECE PROCESSING SYSTEMS AND ASSOCIATED METHODS OF COLOR CORRECTION
[patent_app_type] => utility
[patent_app_number] => 18/464789
[patent_app_country] => US
[patent_app_date] => 2023-09-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 4846
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -10
[patent_words_short_claim] => 155
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18464789
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/464789 | MICROELECTRONIC WORKPIECE PROCESSING SYSTEMS AND ASSOCIATED METHODS OF COLOR CORRECTION | Sep 10, 2023 | Abandoned |
Array
(
[id] => 18866165
[patent_doc_number] => 20230420602
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-12-28
[patent_title] => MICROELECTRONIC WORKPIECE PROCESSING SYSTEMS AND ASSOCIATED METHODS OF COLOR CORRECTION
[patent_app_type] => utility
[patent_app_number] => 18/464789
[patent_app_country] => US
[patent_app_date] => 2023-09-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 4846
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -10
[patent_words_short_claim] => 155
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18464789
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/464789 | MICROELECTRONIC WORKPIECE PROCESSING SYSTEMS AND ASSOCIATED METHODS OF COLOR CORRECTION | Sep 10, 2023 | Abandoned |
Array
(
[id] => 19349390
[patent_doc_number] => 20240258354
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-08-01
[patent_title] => IMAGE SENSOR AND ELECTRONIC SYSTEM INCLUDING THE SAME
[patent_app_type] => utility
[patent_app_number] => 18/242597
[patent_app_country] => US
[patent_app_date] => 2023-09-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 21197
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 166
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18242597
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/242597 | IMAGE SENSOR AND ELECTRONIC SYSTEM INCLUDING THE SAME | Sep 5, 2023 | Pending |
Array
(
[id] => 18865846
[patent_doc_number] => 20230420283
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-12-28
[patent_title] => METHODS FOR PRODUCING A 3D SEMICONDUCTOR DEVICE AND STRUCTURE WITH MEMORY CELLS AND MULTIPLE METAL LAYERS
[patent_app_type] => utility
[patent_app_number] => 18/241990
[patent_app_country] => US
[patent_app_date] => 2023-09-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 80074
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 228
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18241990
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/241990 | Methods for producing a 3D semiconductor device and structure with memory cells and multiple metal layers | Sep 3, 2023 | Issued |
Array
(
[id] => 19239439
[patent_doc_number] => 20240196635
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-06-13
[patent_title] => SENSOR EMBEDDED DISPLAY PANEL AND ELECTRONIC DEVICE
[patent_app_type] => utility
[patent_app_number] => 18/459942
[patent_app_country] => US
[patent_app_date] => 2023-09-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 19373
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 258
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18459942
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/459942 | SENSOR EMBEDDED DISPLAY PANEL AND ELECTRONIC DEVICE | Aug 31, 2023 | Pending |
Array
(
[id] => 18835312
[patent_doc_number] => 20230403839
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-12-14
[patent_title] => SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME
[patent_app_type] => utility
[patent_app_number] => 18/455980
[patent_app_country] => US
[patent_app_date] => 2023-08-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 13246
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 190
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18455980
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/455980 | Method of manufacturing a semiconductor device having a node capping pattern and a gate capping pattern | Aug 24, 2023 | Issued |
Array
(
[id] => 18835312
[patent_doc_number] => 20230403839
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-12-14
[patent_title] => SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME
[patent_app_type] => utility
[patent_app_number] => 18/455980
[patent_app_country] => US
[patent_app_date] => 2023-08-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 13246
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 190
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18455980
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/455980 | Method of manufacturing a semiconductor device having a node capping pattern and a gate capping pattern | Aug 24, 2023 | Issued |
Array
(
[id] => 19829997
[patent_doc_number] => 12250804
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-03-11
[patent_title] => SRAM cell layout including arrangement of multiple active regions and multiple gate regions
[patent_app_type] => utility
[patent_app_number] => 18/454471
[patent_app_country] => US
[patent_app_date] => 2023-08-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 10
[patent_no_of_words] => 12458
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 185
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18454471
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/454471 | SRAM cell layout including arrangement of multiple active regions and multiple gate regions | Aug 22, 2023 | Issued |
Array
(
[id] => 18812884
[patent_doc_number] => 20230387221
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-11-30
[patent_title] => SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURE
[patent_app_type] => utility
[patent_app_number] => 18/447053
[patent_app_country] => US
[patent_app_date] => 2023-08-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 11565
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 56
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18447053
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/447053 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURE | Aug 8, 2023 | Pending |
Array
(
[id] => 18812657
[patent_doc_number] => 20230386994
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-11-30
[patent_title] => SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THEREOF
[patent_app_type] => utility
[patent_app_number] => 18/446873
[patent_app_country] => US
[patent_app_date] => 2023-08-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 12756
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 132
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18446873
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/446873 | Middle end of line decoupling capacitors for semiconductor devices and methods of manufacturing thereof | Aug 8, 2023 | Issued |
Array
(
[id] => 18791140
[patent_doc_number] => 20230380126
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-11-23
[patent_title] => DUMMY METAL BONDING PADS FOR UNDERFILL APPLICATION IN SEMICONDUCTOR DIE PACKAGING AND METHODS OF FORMING THE SAME
[patent_app_type] => utility
[patent_app_number] => 18/230782
[patent_app_country] => US
[patent_app_date] => 2023-08-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 9347
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 118
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18230782
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/230782 | Dummy metal bonding pads for underfill application in semiconductor die packaging and methods of forming the same | Aug 6, 2023 | Issued |
Array
(
[id] => 20119650
[patent_doc_number] => 12369389
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-07-22
[patent_title] => Integrated circuit in hybrid row height structure
[patent_app_type] => utility
[patent_app_number] => 18/361722
[patent_app_country] => US
[patent_app_date] => 2023-07-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 19
[patent_figures_cnt] => 25
[patent_no_of_words] => 8991
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 217
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18361722
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/361722 | Integrated circuit in hybrid row height structure | Jul 27, 2023 | Issued |
Array
(
[id] => 18774454
[patent_doc_number] => 20230369285
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-11-16
[patent_title] => METHOD OF FABRICATING A SEMICONDUCTOR CHIP HAVING STRENGTH ADJUSTMENT PATTERN IN BONDING LAYER
[patent_app_type] => utility
[patent_app_number] => 18/359825
[patent_app_country] => US
[patent_app_date] => 2023-07-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 6625
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 109
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18359825
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/359825 | Method of fabricating a semiconductor chip having strength adjustment pattern in bonding layer | Jul 25, 2023 | Issued |
Array
(
[id] => 19885403
[patent_doc_number] => 12271116
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-04-08
[patent_title] => Method of measuring mask overlay using test patterns
[patent_app_type] => utility
[patent_app_number] => 18/357220
[patent_app_country] => US
[patent_app_date] => 2023-07-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 13
[patent_no_of_words] => 11242
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 206
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18357220
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/357220 | Method of measuring mask overlay using test patterns | Jul 23, 2023 | Issued |
Array
(
[id] => 19670823
[patent_doc_number] => 12183592
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2024-12-31
[patent_title] => Method of manufacturing a ceramic structure with metal traces
[patent_app_type] => utility
[patent_app_number] => 18/224524
[patent_app_country] => US
[patent_app_date] => 2023-07-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 10
[patent_no_of_words] => 5803
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 152
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18224524
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/224524 | Method of manufacturing a ceramic structure with metal traces | Jul 19, 2023 | Issued |
Array
(
[id] => 18913025
[patent_doc_number] => 11876011
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2024-01-16
[patent_title] => 3D semiconductor device and structure with single-crystal layers
[patent_app_type] => utility
[patent_app_number] => 18/215062
[patent_app_country] => US
[patent_app_date] => 2023-06-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 90
[patent_figures_cnt] => 356
[patent_no_of_words] => 79701
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 132
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18215062
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/215062 | 3D semiconductor device and structure with single-crystal layers | Jun 26, 2023 | Issued |
Array
(
[id] => 19814006
[patent_doc_number] => 12245436
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-03-04
[patent_title] => Device structure including field effect transistors and ferroelectric capacitors
[patent_app_type] => utility
[patent_app_number] => 18/341793
[patent_app_country] => US
[patent_app_date] => 2023-06-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 15
[patent_no_of_words] => 9525
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 167
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18341793
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/341793 | Device structure including field effect transistors and ferroelectric capacitors | Jun 26, 2023 | Issued |